Re: bf506 TIMER_width and TIMER_Period for AD sample rate

Hi, Prashant

my codes is based on http://ez.analog.com/message/46731#46731

yes, my question is the sampling rate of internal ADC controlled through ACM, but from the codes, i am confused on the sampling rate of ADC.

Thanks.

codes:

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#include <stdio.h>

#include "ccblkfn.h"

#include "sys/exception.h"

#include <blackfin.h>

#include "cdefBF506F.H"

#define TMODE(val) val

#define bufsize 5000

EX_INTERRUPT_HANDLER(EVENT_STATUS_INTERRUPT);

EX_INTERRUPT_HANDLER(Sport1_RX_ISR);

EX_INTERRUPT_HANDLER(Timer7_ISR);

short int Rx_Buffer[bufsize],ADC_val;

int count=0,trigcount,Rx_flag;

int i=0,dmadone,T,N;

int y=0;

void main( void )

{

          //ClkIn = 25MHz

          *pPLL_CTL = 0x1E00;//VCO = 16*ClkIn = 400MHz

          *pPLL_DIV = 0x0005;//SCLK = VCO/4 = 100MHz

          i = cli();

          idle();

          sti(i);

          register_handler(ik_ivg9, Sport1_RX_ISR);

          register_handler(ik_ivg10, EVENT_STATUS_INTERRUPT);

          register_handler(ik_ivg12, Timer7_ISR);

          *pSIC_IMASK0 = 0x00040000;

          *pSIC_IMASK1 = 0x00010080;

          *pPORTG_FER = PG5 | PG6 | PG7 | PG8 | PG9 | PG10 | PG11;

          *pPORTG_MUX = 0x0040;

          *pPORTH_FER |= PH0 | PH1 | PH2;

          //Timer7 Config for trigger

          *pTIMER7_CONFIG = PERIOD_CNT | PWM_OUT | PULSE_HI;// | IRQ_ENA;

          *pTIMER7_PERIOD = 128;//Sampling freq = SCLK / Period

          *pTIMER7_WIDTH = 5;

/****************************************************************/

/***WAVEFORM GENERATION USING TIMER0*****************************/

/****************************************************************/

          *pPORTG_FER |= PG14;

          *pPORTG_MUX |= 0x8000;

          //Timer0 Config for trigger

          *pTIMER0_CONFIG = PERIOD_CNT | PWM_OUT | EMU_RUN ;

          *pTIMER0_PERIOD = 64000;

          *pTIMER0_WIDTH = 32000;

          *pTIMER_ENABLE = TIMEN0;

//          *pDMA4_CONFIG = WNR | WDSIZE_16 | DI_EN;

//          *pDMA4_X_COUNT = bufsize;

//          *pDMA4_START_ADDR = (void*)Rx_Buffer;

//          *pDMA4_X_MODIFY = 2;

          *pSPORT1_RCR2 = SLEN(11);

          *pSPORT1_RCR1 = RCKFE | LRFS | RFSR | 0x4;//Sign extended

          T = 100;

          N = 1;

          *pACM_ET0 = 0;

          *pACM_ER0 = 0x31;//single, 2Vref, channel 1

/*

          N = 2;

          *pACM_ET1 = 10 + T;

          *pACM_ER1 = 0x21;//single, 1Vref, channel 1

          N = 3;

          *pACM_ET2 = 10 + 2*T;

          *pACM_ER2 = 0x21;//single, 1Vref, channel 1

          N = 4;

          *pACM_ET3 = 10 + 3*T;

          *pACM_ER3 = 0x21;//single, 1Vref, channel 1

          N = 5;

          *pACM_ET4 = 10 + 4*T;

          *pACM_ER4 = 0x21;//single, 1Vref, channel 1

          N = 6;

          *pACM_ET5 = 10 + 5*T;

          *pACM_ER5 = 0x21;//single, 1Vref, channel 1

          N = 7;

          *pACM_ET6 = 10 + 6*T;

          *pACM_ER6 = 0x21;//single, 1Vref, channel 1

          N = 8;

          *pACM_ET7 = 10 + 7*T;

          *pACM_ER7 = 0x21;//single, 1Vref, channel 1

          N = 9;

          *pACM_ET8 = 10 + 8*T;

          *pACM_ER8 = 0x21;//single, 1Vref, channel 1

          N = 10;

          *pACM_ET9 = 10 + 9*T;

          *pACM_ER9 = 0x21;//single, 1Vref, channel 1

          N = 11;

          *pACM_ET10 = 10 + 10*T;

          *pACM_ER10 = 0x21;//single, 1Vref, channel 1

          N = 12;

          *pACM_ET11 = 10 + 11*T;

          *pACM_ER11 = 0x21;//single, 1Vref, channel 1

          N = 13;

          *pACM_ET12 = 10 + 12*T;

          *pACM_ER12 = 0x21;//single, 1Vref, channel 1

          N = 14;

          *pACM_ET13 = 10 + 13*T;

          *pACM_ER13 = 0x21;//single, 1Vref, channel 1

          N = 15;

          *pACM_ET14 = 10 + 14*T;

          *pACM_ER14 = 0x21;//single, 1Vref, channel 1

          N = 16;

          *pACM_ET15 = 10 + 15*T;

          *pACM_ER15 = 0x21;//single, 1Vref, channel 1

*/

//          *pACM_EMSK = 0x0001;

//          *pACM_IMSK = 0x0001;

          //CSW = 14 AClk cycles

          //HC = 0 Aclk cycles

          //ZC = 2 Aclk cycles

          //Setup = 1 Sclk cycle

          *pACM_TC1 = 0x200D;

          *pACM_TC0 = 0x0001;//ADCLK = SCLK / 2/(CKDIV+1) = 31.25MHz

          //Sport 1

          //clk polarity falling edge

          //active low CS

          //rising edge for ACM-timer0

          //ACM timer0 enabled with TMR7 external trigger

          *pACM_CTL = 0x401A;

          *pACM_CTL |= 0x01;//enable ACM

//          *pDMA4_CONFIG |= DMAEN;//enable DMA4(sport1 rx)

          *pSPORT1_RCR1 |= RSPEN;//enable sport1 rx

//          for( i = 0 ; i < 0x3F ; i++ )

//          {

//                    asm("NOP;");

//          }

          *pTIMER_ENABLE = TIMEN7;//enable timer7 for trigger

          while(1)

          {

                    while(Rx_flag==0);

                    Rx_Buffer[y]=ADC_val;

                    if(y<5000)

                              y++;

                    else

                              y=0;

                    Rx_flag=0;

                    *pSPORT1_RCR1 = 0;

//          *pDMA4_CONFIG = 0;

                    *pACM_CTL = 0;

          }

}

EX_INTERRUPT_HANDLER(EVENT_STATUS_INTERRUPT)

{

          *pACM_ES = *pACM_ES;

          ssync();

}

EX_INTERRUPT_HANDLER(Sport1_RX_ISR)

{

           ADC_val = *pSPORT1_RX16;//storing 12-bit ADC value from Sport into 'ADC_val' variable

         Rx_flag = 1;//Indicates that Sport received a data

         ssync();

}

EX_INTERRUPT_HANDLER(Timer7_ISR)

{

          *pTIMER_STATUS = TIMIL7;

          trigcount++;

          if(trigcount == (bufsize / N))

          {

                    *pTIMER_DISABLE = TIMDIS7;

                    ssync();

          }

          ssync();

}