Thanks, Rejeesh. I decided to play it safe and use ISE 14.4 and "Regenerate all project IP (under current project settings)". I then followed the instructions in http://wiki.analog.com/resources/eval/user-guides/ad-fmcomms2-ebz/reference_hdl and generated the ngc and v files, and copied them to the right directories as per the instructions.
After doing this, I opened XPS, opened the project in cf_ad9361_zed/system.xmp, and clicked on Hardware -> Generate bitstream to create a system.bit file. However, this led to an error. I am attaching the platlen.log file and also enclosing the last part of this log file in this email below, which shows the errors. How can I fix this error?
Thanks,
Rahul
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Running UPDATE Tcl procedures for OPTION SYSLEVEL_UPDATE_PROC...
Running system level DRCs...
Performing System level DRCs on properties...
Running DRC Tcl procedures for OPTION SYSLEVEL_DRC_PROC...
WARNING:EDK - ****************************************************************
WARNING:EDK - Optimization Alert: axi_interconnect axi_interconnect_2: One or
WARNING:EDK - more SI or MI slots uses register slices configured as
WARNING:EDK - "Fully-registered" on their AW, AR or B channels
WARNING:EDK - (C_S/M_AXI_AW/AR/B_REGISTER = 1). These control channels
WARNING:EDK - generally cannot take advantage of fully-registered performance.
WARNING:EDK - To reduce resources, use "Light-weight" reg-slices on AW, AR or
WARNING:EDK - B channels (C_S/M_AXI_AW/AR/B_REGISTER = 7).
WARNING:EDK - ****************************************************************
WARNING:EDK - Optimization Alert: axi_interconnect axi_interconnect_3: One or
WARNING:EDK - more SI or MI slots uses register slices configured as
WARNING:EDK - "Fully-registered" on their AW, AR or B channels
WARNING:EDK - (C_S/M_AXI_AW/AR/B_REGISTER = 1). These control channels
WARNING:EDK - generally cannot take advantage of fully-registered performance.
WARNING:EDK - To reduce resources, use "Light-weight" reg-slices on AW, AR or
WARNING:EDK - B channels (C_S/M_AXI_AW/AR/B_REGISTER = 7).
Chipscope Integrate Controller, instance 'chipscope_icon', exists in System
Chipscope Integrate Controller, instance 'chipscope_icon', exists in System
Running UPDATE Tcl procedures for OPTION PLATGEN_SYSLEVEL_UPDATE_PROC...
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_0.
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_1.
ERROR:EDK:2951 -
Unknown Tcl procedure ::hw_axi_ad9361_v1_00_a::run_coregen called
ERROR:EDK - axi_ad9361_0 (axi_ad9361) -
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_2.
INFO: No asynchronous clock conversions in axi_interconnect axi_interconnect_3.
ERROR:EDK:440 - platgen failed with errors!
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