Initially, hardware SPI driver was used. This driver are capable to communicate at 2.0 and 2.6 MHz. But result was the same.
Additionally, this driver clocks SCLK only if I send some data. To wait first 6 cycles I need to send something. But there's no 20 bit SPI packet mode in current implementation. I need to use few transactions (3x8bit or 2x16bit or even 4x5bit) to perform full reading sequence. Is delay on SCLK between transaction also can be a source of problems? I can make some screenshots for hardware SPI communications.
I didn't check yet the quality of signals. Will perform it soon.