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Re: Receiver for Analog Front end reduced range lvds output

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The ADDI7013 specifies 200mV typical for the differential output swing, but the minimum can be less than 200mV. I don't know what the FPGA's receiver threshold is, whether this is OK or not.

 

Yes, the ADDI7013 can also operate at 20 MHz or 30 MHz pixel rates.


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