Hello Michael,
We are transmitting from one ad9361 and receiving from another. So, we
1) Removed Y101 crystal from one ad9361 (acting as receiver)
2) Tapped the CLK_OUT pin of other ad9361 (acting as transmitter) and giving it to the REF_CLK (J105)port of the receiving ad9361.
We made these changes in the NO_OS
1) xo_disable_use_ext_refclk_enable This parameter is set as 1 in the receiving side(no crystal)
2)clk_output_mode_select This paramter is set as 1 in the transmitting side (with crystal)
With the above changes, we are able to receive and decode properly.
When the Linux is running on the Zynq board,
1)adi,xo-disable-use-ext-refclk-enable; This parameter is set as 1 in the dts file of receiver(no crystal)
2)adi,clk-output-mode-select=<0x1>; This line is added In the dts file of the transmitter(ad9361 with crystal)
Do we need to make any other changes in the dts files to make it work?
Also, we are planning to use 10MHZ external clock for both of the ad9361 s through Ettus Octaclock-g. Do we need to make any additional changes before starting with this?
