Hi Soumya-
1) The SYSREF signal is only needed for subclass 1 operation of the JESD204B interface for deterministic latency. The SYSREF signal does not need to be generated from the same source as the sample clock. However, since it should be source synchronous to the clock for sample accurate deterministic latency, the best choice is to have SYSREF generated from the same source as the sample clock.
2) SYSREF will need to be a harmonic of the LMFC frequency. This frequency will be established from the samples per frame and the frames per multi-frame parameter settings for JESD204B within the AD9625. The maximum frequency can not be faster than the LMFC. Since SYSREF could be a single pulse, there is not a minimum frequency.
3) The minimum differential voltage for SYSREF on the AD9625 is 250mVpp. The power can be split from the source, as long as the minimum Vswing is maintained at the SYSREF input to the AD9625.
Thanks,
Ian Beavers