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Re: ADN2915 CDR in LTD mode

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Dear Mr. Lee,

 

Thank you for being interested in ADN2915. Here are some initial answers to your questions:

 

    1. Pictures below are showing data output eye diagram from ADN2915 In LTD mode. 

         When input is 6.144G, output eye diagram is good. However output eye diagram is moving back and forth when

        10.312G. According to my test, frequency higher than 9G shows eye diagram which seems not to be triggered.

        Is any additional setting needed for high frequency?  With ADN2915 configured in power-on default value,

        it was tested.

 

QA:     Have you checked your scope trigger frequency operation range? If yes, what it is?

           In LTD mode, ADN2915 will output a recovered clock frequency in a half rate of the input siganl. For example,

          when input signal is at 10Gbps, the recovered output clock frequency is 5GHz. If you use this recovered clock     

          as the scope trigger and the clock frequency excessed the trigger operation range, you would see the jittery

          impact as you observed.

 

          If your setup is different from the way we discussed above, please specify.

 

  2. Is it possible to implement PPG(Pulse Pattern Generator) and ED(Error Detection) at the same time with only a single ADN2915?  Do I need to use 2 ADN2915s for the respective function?

 

QA:     ADN2915 can be configured either a PPG, or a ED at a time. So, you need two ADN2915s, one for PPG, and another one for ED to own both functions at the same time.

 

     3. Can cross point postion of eye diagram be adjustable by a user?

 

QA:     No. Why do you need to adjust the output eye cross point?

 

Hope these are useful to your ADN2915 evaluation.

 

Best Regards,

 

Dongfeng Zhao


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