Hi There Richard...
Interesting question...have you considered (or already tried) configuring the port pin (PG0 or PG13) as a GPIO pin? On that processor, the slave-select inputs for the SPIs are enabled by the SPI modules themselves by virtue of enabling the SPI in slave mode with the PSSE bit set. This configuration trumps anything set explicitly in the PORTG_FER and PORT_MUX registers...I don't know for certain, but it COULD be the case that if you configure the pin as an input GPIO and set up an interrupt on rising edge, you might be able to trigger a GPIO interrupt when the chip-select goes away...if not, then you could achieve the same if you had a free GPIO pin that you could connect externally to the PG0 or PG13 pin (depending on which SPI you are using), and then utilize THAT pin as a GPIO input capable of generating a positive-edge sensitive interrupt request.
-Joe