I'm reading all 8 channels in 144 SCLK cycles. Both SCLK and CS generated by a CPLD from a common 25MHz clock, SCLK running continuously at 12.5MHz, CS synchronous with SCLK rising edges, data bits latched on SCLK falling edges. The problem is that the MSB of V1 is missing, and remaining data bits are shifted left. The datasheet (page 25) says: "This MSB is valid on the first falling edge of the SCLK after the CS falling edge" but it does not seem to be the case, the SCLK rising edge synchronous with CS falling edge already clocks out the next bit when it shouldn't (as there was no "first falling edge of the SCLK after the CS falling edge" yet). Figure 6 on page 9 suggests SCLK should go high "just before" CS goes low, but there is no spec how long "just before" is. I was able to work around this by gating SCLK with CS in the CPLD (SCLK stays high when CS inactive), and then it works as expected (data looks good on a scope, and is also correctly read by ADSP-BF537 SPORT in TDM mode). But I think this corner case (CS synchronous with SCLK rising edges) should be documented and have some timing specs, and the sentence about "first falling edge of the SCLK after the CS falling edge" might need to be corrected. Has anyone else seen similar issues?
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