1) C21 should be 1nF, not 100nF
2) Not sure why you have R464,468,469 & 470. YC and RGB selection can use the input mux of the 7181. Deosn't hurt
3) HS an CS are inputs, normally from PC RGB sources. For this design you are relying on SoG/SoY so these pins are not used at all. They can be pulled to ground.
4) Note, you've set up the output for OF_SEL = 0010 16-bit 4:2:2 or OF_SEL = 0011, 8-bit 4:2:2. Might be able to do RGB output but you would have to handle DDR clocking
5) Best to use solid ground plane, don't split ground like Figure 78
6) If this is for extended temperature range use NPO caps for C36 and C37
7) I know the reference schematic doesn't do it but it is nice to use and LC power rail filter for PVDD_1.8V. This rail should be keep very clean. It doesn't hurt to LC filter the other power rail either. I use a Murrata NFM21PC105B1A3 instead of an inductor.
8) LLC pin needs a series resistor?
9) FB pin is not used unless you are planning to do fast switching between RGB and YC
10) Check the crystal load capacitors against the formula in the data sheet.