Hi All,
I'm trying to port U-boot on a custom board, trying to run UART_BOOT. Board is similar to bf537-stamp so used and modified bf537-stamp.c and bf537-stamp.h. Instead of 64mB we have 32mB SDRAM. CLK settings done as per SDFC Calculations. File attached.
| #define CONFIG_BFIN_CPU | bf537-0.3 |
| #define CONFIG_BFIN_BOOT_MODE | BFIN_BOOT_UART |
/*
* Clock Settings
* CCLK = (CLKIN * VCO_MULT) / CCLK_DIV
* SCLK = (CLKIN * VCO_MULT) / SCLK_DIV
*/
/* CONFIG_CLKIN_HZ is any value in Hz */
#define CONFIG_CLKIN_HZ 25000000
/* CLKIN_HALF controls the DF bit in PLL_CTL 0 = CLKIN */
/* 1 = CLKIN / 2 */
#define CONFIG_CLKIN_HALF 0
/* PLL_BYPASS controls the BYPASS bit in PLL_CTL 0 = do not bypass */
/* 1 = bypass PLL */
#define CONFIG_PLL_BYPASS 0
/* VCO_MULT controls the MSEL (multiplier) bits in PLL_CTL */
/* Values can range from 0-63 (where 0 means 64) */
#define CONFIG_VCO_MULT 20
/* CCLK_DIV controls the core clock divider */
/* Values can be 1, 2, 4, or 8 ONLY */
#define CONFIG_CCLK_DIV 1
/* SCLK_DIV controls the system clock divider */
/* Values can range from 1-15 */
#define CONFIG_SCLK_DIV 4
/*
* Memory Settings
*/
#define CONFIG_MEM_ADD_WDTH 9
/* Changed mem size 16M16 instead of 32M16(64) */
#define CONFIG_MEM_SIZE 32
#define CONFIG_EBIU_SDRRC_VAL 0x026B
#define CONFIG_EBIU_SDGCTL_VAL 0x80911109
#define CONFIG_EBIU_SDBCTL_VAL 0x0013
#define CONFIG_EBIU_AMGCTL_VAL 0xFF
#define CONFIG_EBIU_AMBCTL0_VAL 0x7BB07BB0
#define CONFIG_EBIU_AMBCTL1_VAL 0xFFC27BB0
#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_MALLOC_LEN (384 * 1024)
| #define CONFIG_UART_CONSOLE | 0 |
#define CONFIG_DEBUG_EARLY_SERIAL 1
Early prints are turned ON. Its seems processor is executing till the end of initcode. Getting '>' the last print in initcode. It seems that U-boot isn't loading in external RAM. I have tried to reduce SCLK, RAM CLK to as low as 40 mhz from 120mhz. Clk is coming properly along with ADDR and DATA bus signals.
As per STAMP schematic with 64mB SDRAM, ABE0 is connected to DQMH(39) of one 32mB SDRAM and ABE1 is connected to other SDRAM chip. Since we have only one 32 mB chip we have connected ABE0 -> DQML and ABE1 -> DQMH of the same chip (like BF518-EZBRD).
Do we need to make changes corresponding to that somewhere? Can anyone guide me where I need to make changes?