Hi,
I worked on my problem. I use the newest version of AXI_DMAC. To test the DMAC core, I designed a counter which generates data valid and data signal. And the counter counts from start value to stop value. The data valid and data is connected to AXI_DMAC FIFO input.
The first 2D transfer finishes successfully. Then, I start a new transfer which is also successful but transferred data is wrong.
Example:
In the first transfer, [1 2 3 4 5 6 7 8] is generated by counter and transferred data is [1 2 3 4 5 6 7 8] correct.
In the second transfer, [1 2 3 4 5 6 7 8] is generated by counter but the transferred data is [8 1 2 3 4 5 6 7] wrong.
The last data of previous transfer makes problem.
I set up the same configuration with the old AXI_DMAC core. The design worked very well.
Example:
In the first transfer, [1 2 3 4 5 6 7 8] is generated by counter and transferred data is [1 2 3 4 5 6 7 8] correct.
In the second transfer, [1 2 3 4 5 6 7 8] is generated by counter but the transferred data is [1 2 3 4 5 6 7 8] correct.
I should use the newest version of DMAC core, because of the new properties.
Is this a bug in the HDL code?
How can I solve this problem?
Thanks,
Muhammet