Hello Harshit,
Thank you very much for your reply, and sorry to take time to respond, since spending time to study HRM you instructed, and chapter of "Synchronous Mode Interface Timing".
At first, I think I have to explain the original cause of the question was whether attached timing signal, /WR strobe when Synchronous Write, is correct or not, which is provided from our customer, driving under following setups.
[External Memory Setup Register]
EB0AM=10, EB0WS=010
(indicating, Read : 2-waitstate, Write : 1-waitstate)
[Clocks]
tCLKIN ： 40ns (CLKIN=25MHz)
tCKOP ： 20ns (CLKOUT=50MHz, by using CLKDBL)
The timing chart shows
≒60ns, from rising edge of /WR strobe to next rising edge.(It may be better to say falling edge since /WR is low active. )
≒40ns, the width of asserted /WR strobe.
Subject to Figure 7-11 and related description of HRM page.475 you indicated, I think the attached timing chart is reasonable and explicable,
but if you kindly confirmed it, it would be very much appreciated.
Thank you again for your notes and subject to the provided information, ACK=High fixed and unchanged, thus I assume the system is using only one processor on the bus.
You may doubt why ask these fundamentals for this legacy device. In fact, this is old system but still work and like as many other cases, original engineer is not already there.
Engineers who inherit to maintain the system has to check from scratch, so the sort of these questions often upwell, as same as the device which is newly released.
These are background and if I receive additional questions, I will add here or create a new thread.
Again, thank you very much for your helps, as always.
Best Regards,