Hi Dave,
I have found out the reason why IRQ or DREQ becomes low after initialization is that ADV212 somehow start to compress data itself before any data input. I use HVF mode to input data and Normal Host mode to read compressed data.HSYNC,VSYNC active falling edge,VCLK active rising edge.The timing sequence after initialization is shown in figure below.
The first IRQ asserts after writing 0x0400 to EIRQIE,then after clear the EIRQFLG,SCOMM[3:0] changes from 0 to 1-2-3-4-5-6-7. There is about 20ms interval between SCOMM[3:0] changes from 7 to 8. My VCLK is 20MHz,valid field size is 640*640. 50ns*640*640=20.48ms,just approximate to the time interval.If I change XTOT and YTOT size,this time interval will change too. You can see about 28ms after initialization,IRQ asserts and SCOMM[3:0] changes from 7 to 8-A-B-C. This must mean that ADV212 somehow trigers to compress,but as shown in the figrue neither HSYNC nor VSYNC is valid.There is no data transfer via VDATA bus.In fact, after the initialozation FPGA holds in a state waiting for command. I read the data in CODEFIFO back and display the file on PC screen. All pixel value is 0. If I don't input VCLK,all these doesn't happen.Please help me understand this.
When I transfer the first pattern in ADV212,IRQ doesn't assert,just as the figure2 shows below.
Then after following pattern transfer, IRQ asserts as figure3 shown below.
Why IRQ doesn't assert after the first transfer? Please help me!!