Here is the code for my dac_interface_top. The wr_clk is driven by a looped back version of rd_clk in wrapper of my block design.
Currently my top level VHDL in my block design wrapper loads data into this dac_interface_top every 4 clocks as you mentioned - and using 2 leds to monitor empty/full I notice the fifo is neither full nor empty so both my code and the util_dac_unpack are reading from this fifo. I am not however seeing any output from either transmitter.
What lines of code must I execute from the dac_init function for this to work properly?
library IEEE; use IEEE.STD_LOGIC_1164.ALL; entity dac_interface_top is Port ( rd_clk : in STD_LOGIC; rd_en : in STD_LOGIC; rd_valid : out STD_LOGIC; rd_data : out STD_LOGIC_VECTOR (63 downto 0); wr_clk : in STD_LOGIC; wr_en : in STD_LOGIC; wr_data : in STD_LOGIC_VECTOR (63 downto 0); full : out STD_LOGIC; empty : out STD_LOGIC); end dac_interface_top; architecture Behavioral of dac_interface_top is component fifo_generator_0 port ( rst : in std_logic; wr_clk : in std_logic; rd_clk : in std_logic; din : in std_logic_vector(63 downto 0); wr_en : in std_logic; rd_en : in std_logic; dout : out std_logic_vector(63 downto 0); full : out std_logic; empty : out std_logic ); end component; constant b0 : std_logic := '0'; begin fifo_inst : fifo_generator_0 port map ( rst => b0, wr_clk => wr_clk, rd_clk => rd_clk, din => wr_data, wr_en => wr_en, rd_en => rd_en, dout => rd_data, full => full, empty => empty ); process(rd_clk) begin if rising_edge(rd_clk) then rd_valid <= rd_en; end if; end process;