Reejesh,
Can you please elaborate on how we should debug this? Looks like irrespective of the DAC Clock Rate (1 or 3), based on the DAC Channel valid, the ADC Pack and DAC Unpack blocks grabs only two channels of data. Because in 1RX1TX mode only two channels are asserted as valid, it words even with DAC Clock Rate set to 3. It would appear that if I set the clock rate to 1 from 3, I would need to update the ADC Pack and DAC Unpack IPs? Can you provide me an answer to this. I want to use a HDL design that has been validated and tested for 1Rx1Tx mode.
