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Re: Square pixel on ADV739X eval brd

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1) Yes, but it needs the 24.54MHz clock

 

FYI: http://ez.analog.com/message/8669#8669

 

2) I am not sure if the FPGA code can generate the 24.54MHz clock from the 27MHz oscillator.  You may have to change the oscillator.  Regardless I am forwarding this to some who knows.


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