I think it's kind of risky. In the ad9361's reference design (pg. 91) says the following:
The DATA_CLK frequency generated depends on the system architecture (such as, number of RF channels, degree of over-sampling, and bandwidth mode).
So it's not a good idea to use the clk_out for the all system, because its frequency depends of the actual device setup.
Did you tried to consult with a Xilinx guy about this issue. I would recommend to open a webcase at Xilinx, maybe they can suggest a more suitable clocking method for you.
Thanks,
Istvan