The 7619 includes interleaved pixel output modes for pixel clocks above 150 MHz, such as "2 x SDR 4:4:4 Interleaved" mode - where the pixel output is 48b wide at 1/2 of the incoming pixel clock rate.
Is there a minimum pixel clock rate for these interleaved modes?
For example - is it possible to take in a 100 MHz pixel clock and use the 2 x SDR 4:4:4 mode resulting in an output clock (LLC) of 50 MHz?