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Re: ADIS16405 communicating with STM32F103CBT6 using SPI

Hi Mark,Thank your for pointing out the error about tstall. I increased the tstall time, but nothing joyful happened. I will take your other suggestions, and check more about the singalsfurther. I...

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Re: 关于bf609buildroot生成的文件系统中用户自定义应用程序的自动执行?

Hi, Aaron      我按照你说的做了,我写了一个shell脚本app_test,用来执行我自定义的程序,然后我把shell脚本保存在/buildroot/output/target/app/下,然后在board/AnalogDevices/blackfin/target_skeleton/etc/rc的最后增加了./app/app_test,可是还是没有执行我的代码,难道是我的脚本写错了?...

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How to improve the speed of reading SD card with BF518

Now ,I use the peripheral which is the RSI. And I configured it with 4-bit SD modes. I  used the file system which is the Petit FatFs. Now DSP read the SD is 1.3M/s. But I want improve the speed, how...

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Re: 关于bf609buildroot生成的文件系统中用户自定义应用程序的自动执行?

very likely you have missed something, you may try to debug by starting from taking a look at the contents of /etc/rc on your target board when it's up.

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Re: How to improve the speed of reading SD card with BF518

The sd card is 4g, class 4. RSI_CLK is 50Mhz.

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Re: 关于bf609buildroot生成的文件系统中用户自定义应用程序的自动执行?

what is your hello file doing? try to do something like "mkdir /tmp/test_dir" in it, instead of print something, I am not sure if the print from rc will be displayed on the console.

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Re: 关于bf609buildroot生成的文件系统中用户自定义应用程序的自动执行?

hi,Aaron!     board/AnalogDevices/blackfin/target_skeleton/etc/rc与/buildroot/output/target/etc/rc有什么区别?

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Re: 关于bf609buildroot生成的文件系统中用户自定义应用程序的自动执行?

The later is generated according to the former, do edit the former instead of the later.

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Re: AD9963-EBZ and Xilinx ML605

Yes, I am configuring the TxCLK pin as an input because I am sending it through "TXCLKI_CMOS" pin in the "FMC adapter", as I have previously explained. I am also sending through "MAIN CLOCK INPUT" SMA...

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some adv212s are not working

hi DAVEi recently bought five adv212 . but only two adv212s are working in my board and compress image data but others are not working anyway. the hardware and software which is written for them is...

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Re: ADF435x software

Hi Rob, Thanks for your quick reply. I've tried the things you suggested, but unfortunately they don't make the sweeping faster. I've also tried using a different port and a different PC: still the...

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Re: ADL5606 matching network for 2400-2485mhz

Any idea?

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Re: ADV7623 OSD Font Question

Hi Chris, About the first question, there is no known problem with Tbox #0 but remember that the Tbox index must be in order from top to bottom and left to right for each video line.  So T-box #0...

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Re: ADXL345 not returning DevID correctly via SPI

RonW, I came across your query while searching for other issues with the ADXL345. Some four years ago I discovered the ADXL345 is terrifically sensitive to ringing on its SDO line when configured for...

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Re: bypassing delay block in ADAU1761

Hi chuck: Would you mind sharing your schematic. This will help all debug your problem. Thank you Miguel

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Re: AD7176-2

Hi Chiranjeevi M, The settling time is the time required for the digital filter to fully settle any step at the input or any data from another channel in the case where multiple channels are used. The...

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Re: AD7714 self-calibration

HI Caleb Pellerin, Can you send me scope shots of your interface lines? Regarding why DIN should be kept high, there's a document on this which states: “The interface implementation on these converters...

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Re: bypassing delay block in ADAU1761

     Hi chuckwin,      When SigmaStudio compiles a project, each block gets an independent allotment of processor time (instructions), parameter storage, and data memory.  The only connections between...

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ADV7393 HSYNC and VSYNC timing diagram for input mode 000

Hello,For the ADV7393, the figure 6 of the datasheet shows the HSYNC and VSYNC timing diagram of SD input, 16-bit 4:4:4 RGB, input Mode 000. Please explain ( or give some reference) the detail of the...

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AD9517 PLL Clock Chip on AD9649 Evaluation Board

Hi, I have a query regarding the AD9649 Evaluation Board.  On the schematics for the board, there is a AD9517-4BCPZ chip included as a clocking option (see attached schematic screenshot), presumably...

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