Hi,
As I can see, if I change the N divider to decrease the PFD frequency, the spurs frequency changes.
The ADF4351 only allows to decrease the PFD to 312.5KHz without warning of change the low spur mode to low noise mode, but this case is worse for my specs. Charge cancellation is enable, Charge pump current is set to 0.31mA and the components of the loop filter are:
C1=33nF
R1=82ohm
C2=1uF
R2=470ohm
C3=5.6nF
I have discovered an "Other functions" tab in ADF435x SW, and if I select VCO Sel = VCO B instead of VCO sel : Normal, the PNoise and ACP decrease! I don´t find literature about this tab, so If someone can help me with this, please, I would be really grateful.
Currently, 10Mhz reference, divider by 25= PFD=400Khz, I have synthesized 340.0125MHz with Chan.spacing= 6.25KHz and I don´t have spurs above -82dBc and ACP@25Khz is -70.9dBc but phase noise is -100dBc/Hz@10KHZ yet.
I am going to narrow my loop filter in order to decrease phase noise, although I suspect my PLL could get a bit unstable.
Any idea to achieve better Phase Noise results without getting worse ACP and spurs results?
Thanks in advance.
Fernando