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Re: ADF4351 PLL lock time and step size

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Using a 1 kHz channel spacing, will allow a PFD frequency of 4 MHz. That will allow you more freedom with your loop bandwidth - up to 400 kHz.

 

I modified Ian's ADIsimPLL file for a 4 MHz PFD and 200 kHz loop bandwidth. This resulted in a <50 µs settling time.

 

ADIsimPLL file attached.


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