Re: ADAU1361, PLL and Fs=32kHz

OK, thank You.

I inattentively read: “The ADCs, DACs, and serial port share a common sampling rate” (p.26). But, in “SERIAL DATA INPUT/OUTPUT PORTS” (p.42-43) nothing said about “R17.CONVSR[2:0]”, only Fs - it confused me…

I saw in your messages “PLL calculator” for ADAU1361/1761 and now “converter control registers” – good tools!

Next question. DataSheet stated (p.27): “The PLL can accept input frequencies in the range of 8 MHz to 27 MHz.” This statement refers to what point - before or after a divider “X” (see fugure 30, p.27)?

Thank You,

Alexander