Re: working with AD-FMCOMMS1 at low sampling rate

Hi Alex,

I thought about a work-around with current 64bit DMA, to make at least 1 channel(I) work correctly by sacrificing independence of the other channel(Q). This will help us a lot until we find a solution to DMAC bit width.

Right now based on your reference design, mapping of the input samples in DAC core is like this:

But if we change the mapping to:

We can send data with proper rate (500MSPS) to one channel. Of course the other channel would be a copy of the first one. But at least we can use one channel with desired rate. Note that in our application we want to use FMCOMMS1 not in the complex IQ mode but we want to use I & Q channel (output of the DAC) as 2 independent outputs (We will not use up-converter chip ADL5375). So this modification makes sense for me.

My question is, whether it is possible to do it JUST by changing the Verilog code "axi_ad9122_core.v", i.e. replacing:

        dac_data_i0 <= dac_ddata[15: 0];

        dac_data_i1 <= dac_ddata[15: 0];

        dac_data_i2 <= dac_ddata[47:32];

        dac_data_i3 <= dac_ddata[47:32];

        dac_data_q0 <= dac_ddata[31:16];

        dac_data_q1 <= dac_ddata[31:16];

        dac_data_q2 <= dac_ddata[63:48];

        dac_data_q3 <= dac_ddata[63:48];

by

        dac_data_i0 <= dac_ddata[15: 0];

        dac_data_i1 <= dac_ddata[31:16];

        dac_data_i2 <= dac_ddata[47:32];

        dac_data_i3 <= dac_ddata[63:48];

        dac_data_q0 <= dac_ddata[15:0];

        dac_data_q1 <= dac_ddata[31:16];

        dac_data_q2 <= dac_ddata[47:32];

        dac_data_q3 <= dac_ddata[63:48];

and rebuild the project or I need another additional modification s in HW?

Of course the SW will be changed correspondingly. But is it the only HW change I need to make before rebuild the project?

Thanks in advance

FArid