No, this is not possible. The architecture features one store bus and two load buses. Please refer to the L1 memory section of the Programmer's Reference manual for details (p6-3):
http://www.analog.com/static/imported-files/processor_manuals/Blackfin_pgr_rev2.2.pdf
What is it that you are doing that requires the memory to be cleared? You might be able to come up with an automated means of doing this by scheduling a Memory DMA that sets the buffer to 0 and using that stream's interrupt to signal the core that the buffer has been cleared.
-Joe