The jitter tolerance of the incoming reference clock for the PLL is pretty much the same for MCLK in or LRCLK in. This has to do with the frequency of the jitter. Low frequency jitter will look like a slowly varying clock and the PLL be able to track it. Very high frequency jitter will be attenuated by the PLL loop filter and not effect the PLL output. So the frequency of the clock has less to do with jitter tolerance of the PLL so the 300ps statement in the ADAU1962 datasheet would apply to the case where LRCLK is the clock source for the PLL.
The PLL in the ADAU1978 is very similar to the PLL in the ADAU1962 so similar jitter tolerance is to be expected.
Thanks,
Dave T.