Thank you. This is excellent. I should have gone to the driver guys first ;-)
To get these 4us and 200us numbers, what is the basic clock frequencies used on the device for this case?
I'm interested in the BPP profile load time as well. A profile load looks like about 20 SPI operations, which is about 100us at 50Mhz SPI clock, so fast tuning would be limited to about that. For >>8 profiles, just swinging between two profiles is probably adequate: are there any caveats loading a profile while using another one?
Regarding the Linux driver, digging through the code I can't see how the _fastlock_ routines, which as all static, are exposed to the rest of the driver system. Normally with virtual drivers these static references as stuck in a structure that is handed off to the higher layers: I'm not finding that. Where can I find the IIO layer code on the ADI website? The code I'm looking at has a July 2014 date on it, so I'm hoping that's new enough.
Our design will involve an FPGA which will eventually do most of the work, and a Linux host outside to do bypass SPI programming through the FPGA implementation has matured. I'm doing lead work on whether this is even feasible...
UPDATE:
Profile 0 looks to be "special"; why is that?
There is mention of a workaround for "lock problem with the same ALC word". Where is this issue documented?
There also looks to be some difference between the behavior of RX even and odd profiles in the recall() logic, so 0 works one way, 1,3,5,7 work another way, and 2,4,6 work a third way:
ad9361_fastlock_recall(0)
ad9361_fastlock_recall: RX Profile 0:
R: 0x236 0x00# REG_RX_FORCE_ALC Force ALC
W: 0x25c 0x0f # REG_RX_FAST_LOCK_PROGRAM_ADDR Fast Lock Program Addr
W: 0x25d 0x02 # REG_RX_FAST_LOCK_PROGRAM_DATA Fast Lock Program Data
W: 0x25f 0x03 # REG_RX_FAST_LOCK_PROGRAM_CTRL Fast Lock Program Control
W: 0x25f 0x00 # REG_RX_FAST_LOCK_PROGRAM_CTRL Fast Lock Program Control
ad9361_fastlock_prepare: RX Profile 0: Prepare
W: 0x25b 0x00 # REG_RX_FAST_LOCK_SETUP_INIT_DELAY Fast Lock Setup Init Delay
W: 0x25a 0x01 # REG_RX_FAST_LOCK_SETUP Fast Lock Setup
W: 0x25f 0x00 # REG_RX_FAST_LOCK_PROGRAM_CTRL Fast Lock Program Control
R: 0x015 0x00# REG_ENSM_CONFIG_2 Config 2
W: 0x015 0x02 # REG_ENSM_CONFIG_2 Config 2
ad9361_trx_vco_cal_control : state 0
R: 0x230 0x00# REG_RX_PFD_CONFIG PFD Config
W: 0x230 0x01 # REG_RX_PFD_CONFIG PFD Config
W: 0x25a 0x01 # REG_RX_FAST_LOCK_SETUP Fast Lock Setup
ad9361_fastlock_recall(1)
ad9361_fastlock_recall: RX Profile 1:
ad9361_fastlock_prepare: RX Profile 1: Prepare
W: 0x25a 0x21 # REG_RX_FAST_LOCK_SETUP Fast Lock Setup
ad9361_fastlock_recall(2)
ad9361_fastlock_recall: RX Profile 2:
W: 0x25c 0x2f # REG_RX_FAST_LOCK_PROGRAM_ADDR Fast Lock Program Addr
W: 0x25d 0x02 # REG_RX_FAST_LOCK_PROGRAM_DATA Fast Lock Program Data
W: 0x25f 0x03 # REG_RX_FAST_LOCK_PROGRAM_CTRL Fast Lock Program Control
W: 0x25f 0x00 # REG_RX_FAST_LOCK_PROGRAM_CTRL Fast Lock Program Control
ad9361_fastlock_prepare: RX Profile 2: Prepare
W: 0x25a 0x41 # REG_RX_FAST_LOCK_SETUP Fast Lock Setup