AD8302 Phase Measurement
HI,I want to use AD8302 board and I want to start characterize the board, I noticed in other discussions that when two signals are exactly the same the phase should be around 900 mv, right? because of...
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Re: Help with rebuilding
I updated to the latest no-OS. Everything works. I'm not sure what I was doing last week that caused me so much trouble, but the latest HDL and no-OS builds are now working. Thanks,--tim
View ArticleADV7842 Level Shifting
Hello, I am looking at the ADV7842 and the audio outputs AP0 to AP5, SCLK, MCLK and i am trying to interface these to an FPGA. The logic level for my FPGA is 1.5V and the logic levels for the...
View ArticleRe: ADV7842 Level Shifting
It is best if you use level shifters. Voh_min = 2.4V and no load resistor was defined for this spec. Also if the resistor divider is too high load impedance you will start seeing RC issues at high...
View ArticleRe: ADV7511 - for dark pixels, the luma values are too bright
The ADV7511 pixel bus is an input bus. It sounds like you have a stuck-at high bit on the board. The 7511 just converts parallel in to serial out. Scope the high luma bit and see if it ever goes low.
View ArticleRe: [AD9984A]/Evaluation Board
Hi Arthur, Do you have a part number for the evaluation board that you received? -Matt
View ArticleRe: [ADV7182] Resistor divider value of AIN pin of ADV7182 with differential...
The sync depth range = 20 - 200% of the nominal value. So if the nominal value is 1Vpp the device can handle 200mVpp at the pin and before the divider network the voltage would be 800mVpp, single...
View ArticleRe: Saturation vs. Overflow
Hi Daniel, There is no need for such an option since any built-in operators for the type fract16, fract2x16 and fract32 use saturating arithmetic by default: #include <fract_math.h> fract16...
View ArticleRe: AD8302 Phase Measurement
Actually the frequency is 2.4 GHz at the two ports and I measured the phase difference for the case the signal is completely reflected, due to presence of coupler phase difference is around 140 instead...
View ArticleRe: no-OS driver, fmcomms1/Common/test.c
If I wanted is122880000 Sample/s dacsamplingrate and122880000 Hz system clock and1966080000 Hz (= 122880000Hz*16) carrier frequency, is it possible to make Xilinx ML605, AD9548, AD9523-1, ADF4351 and...
View ArticleRe: AD9523-1 jitter and phase lock
Is there some intentional dithering on FMCOMMS1 reference designwhich I could disable and make the ML605 and FMCOMMS1 all synchronous?
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Re: ad9361 - some estimate on tuning time (standard and fastlock)
Thank you. This is excellent. I should have gone to the driver guys first ;-) To get these 4us and 200us numbers, what is the basic clock frequencies used on the device for this case? I'm interested in...
View ArticleSigmaStudio simulation
Hi. I am working with version 3.1 of SigmaStudio and am interested in using the ADAU1761 in an application that would look at responses from DC to 10Hz. I have started working with the tutorials and...
View ArticleRe: ADIS16251 vs. ADIS16265 Performance
Thanks! This certainly does help. I'll repeat the test for both sensors this time sampling at the highest possible rate with your filter settings and I'll let you know how it turns out.
View ArticleRe: ADIS16251 vs. ADIS16265 Performance
We look forward to your results. Thank you for sharing them in this discussion.
View ArticleRe: Setting LO frequency taking 40-60ms with libiio
Lars, I applied the patch, but it didn't seem to make any difference. BTW, I used the following sequence of commands to build and apply the change. Let me know if I missed anything. I'm certainly no...
View Articlead9361 201407xx util.c - careful about mixing with a real Linux environment
The ad9361 util.c includes a function __ffs() which returns the first LSB bit that is set using a 0-base notation. This function mirrors the BSD function ffs() and the GLIB 2.0 implementation with the...
View ArticleRe: Setting LO frequency taking 40-60ms with libiio
Are you seeing these delays regardless from the frequency step size?There are in fact some more things related to frequency changes.By default if you tune TX more than 100MHz apart it does a QUAL cal...
View ArticleRe: ad9361 - some estimate on tuning time (standard and fastlock)
Vielen dank fuer alles. The recommended calibrations are in Table 1 Pg 6 of UG570 Rev 0. "Everything was done with the code being posted." is the answer to the question. The documentation recommends...
View ArticleADV7391 horizontal sync time for SMPTE-170M
Hello, I'm using an ADV7391 to generate a 640x480 active image area conforming to the SMPTE-170m standard with only monochrome data. To do this, I've configured the device to use square pixels with...
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