Hi Edd,
What SPI clock rate are you running at?
A block diagram showing the SPI master and slave, the LVDS drivers/receivers and the cable would be helpful, as Reinhard has mentioned, the MISO line will need the LVDS driver at the other end of the cable.
An oscilloscope plot showing the 4 SPI lines at the master, and at the slave, both before and after LVDS driver/receiver, would be useful to understand how timing is being affected.
The description of a different in propagation delay for rising and falling edges sounds like there might be pulse skew introduced by some part of the signal chain. The ADN4665 datasheet specifies a maximum pulse skew of 400 ps and channel-to-channel skew of 500 ps, which are probably small numbers in terms of your clock period or bit time.
There could be skew introduced by the cable, not just propagation delay - e.g. all four pairs may not be exactly the same length, and with twisted pair and such a long cable, maybe even differences within a pair (this will definitely cause pulse skew!)
What part is used for the LVDS receiver?
Regards,
Conal