Hi,
Thanks for this inquiry. You are indeed right. There seems to be a conflict with the information in the datasheet.
To clear things, kindly refer to the truth table provided below for the correct bit assignment and corresponding SYNC_OUT pin output:
Sync_out enable bit CFR2[9] | Sync out/in mux enable bit CFR2[8] | SYNC_OUT pin output | |
WITH SYNC_IN input | WITHOUT SYNC_IN input | ||
0 | 0 | Output is taken from signal at SYNC_IN pin | 3.3V DC |
0 | 1 | Output is taken from signal at SYNC_IN pin | 3.3V DC |
1 | 0 | No output | No output |
1 | 1 | Output is taken from SYNC_OUT generator SYNC_OUT = SYSCLK/384 | Output is taken from SYNC_OUT generator SYNC_OUT = SYSCLK/384 |