hello sir..
I have followed the instructions as told by you in the following link using VIVADO 13.4
https://github.com/analogdevicesinc/hdl
http://wiki.analog.com/resources/fpga/docs/hdl#building_on_vivado
I have added all the libraries in the tcl console....the design is synnthesized, netlist generated and vivado sreen closes automatically
In the software setup for vivado it is mentioned that
- After building the project on vivado for the used FPGA board, a SDK_Export folder will be created in ../fmcomms1_board.sdk/SDK
No such folder is created for me..But i continued following the steps and i got problem in selecting .xml file in new hardware project window..where will be my .xml file located???..help me sir..bit files are generated and i am able to dump them in fpga...but i can't get this .xml and debug_nets.ltx..in the hardware manager while trying to view the signals..what about this SDK_Export folder????....while adding libraries in tcl console and after running projects...the design is synthesized successfully and the vivado gets closed automatically...should i have to do any steps to export the SDK???..hope to hear from u sir...
help me sir..