Hey Rejeesh... Thanks for your reply...
I am sure about 30MHz comes from FPGA and your drivers... I use no-OS.
Please have a look on AD-FMCOMMS1-EBZ Functional Overview [Analog Devices Wiki] diagram (Reference Clock Generator generate 30MHz).
Secondly, I worked on the scenario to have 20MHz generated from AD9548 to AD9523 and it seems the signal is OK but the first PLL of AD9523-1 is not locked... I am not sure if it is because the input 20MHz signal generated by AD9548 or something inside AD9523-1.
In summary, this is the parameter I chose for profile0 in the Excel file of AD9548 evaluation software:
System Clock: 768MHz
Nominal Reference Period: 30MHz
R: 125
S: 335
U: 0
V: 1
And I kept the rest as default.
The first problem is that I do not understand why the calculated DDS frequency is 80.400MHz which should be 80MHz regarding to DDS frequency formula on page 33 of AD9548... Changing FTW to appropriate one, interestingly, checking by spectrum I have a good 80MHz ... I am not sure if the phase is good too.
About AD9523-1 I changed as below:
vcox_freq: 80000000
pll2_ndiv_a_cnt: 2
pll2_ndiv_b_cnt: 9
pll2_freq_doubler: 0
pll2_r2_div: 1
pll2_vco_diff_m1: 4
pll2_vco_diff_m2: 4
The rest are remained as default. It cause the VCo in hte second PLL turn to 3040MHz. Measuring the frequencies by oscilloscope, It generate the clocks as expected but the first PLL is not lock when AD9523_READBACK_0 is read.
Ehsan