i have done the following things :
(1) I opened the HDL design.
(2) I export the HDL design from Xilinx Platform Studio to SDK.
(3) I created a new application project.
(4) I copy the downloaded source files into src folder of the just created empty application.
(5) I increase the Heap Size value (0x400 -> 0x4000)
(6)i downloaded the bit and bmm files to the device,then i run the app,
i set the parameters as wiki said:
As an alternative an UART terminal can be used to capture the output of the example program. The number of used UART port depends on the computer's configuration. The following settings must be used in the UART terminal:
Baud Rate: 115200bps
Data: 8 bit
Parity: None
then i saw something strange:
why?
wish your answer soon!