Clik here to view.
Re: ADIS16251 Screw Torque and Bias
In general, MEMS gyroscope's bias is sensitive to change in its package stress profile, which can happen through tightening the screws down on the PCB. So, this is not a large surprise.
View ArticleRe: Queries about AD8372
Hi, Steve Nice to talk with you and thanks so for your reply.My timings are attached for your reference. After debug, I can write and read the gain code correctly through the timing. But the gain is...
View ArticleRe: AD5422 Read Register in Daisy-chain configuration
Hi, If you have any further questions, please let me know. Otherwise, could you close this thread by selecting the correct answer please. Regards,Mark
View ArticleClik here to view.
question about ADV7125 mininal input clock pulse width @ 165MHz input freq
the ADV7125 datasheet, about the clock pulse width, defined as below table By the table, we can get below information, when fclk_max=140MHz, the minial clock pulse width is 2.85ns, when...
View ArticleRe: Questions about ADV7625 clock, the minimal pulse width@fmax=165MHz
sorry for big typo, the number in this list is ADV7125, I've raised another discussion, please ignore this one, sorry for confusing you.
View ArticleRe: AD8177 AD8175 design support files
Hi, Freddy. I had attached the schematic of AD8175/AD8177 evaluation board. I'm still looking for the software and user guide. I'll get back to you. Regards,Anna
View ArticleAD9601-250EBZ schematics
Hello, I can see the schematics of evaluation board on P.25 of datasheet.But I'm confusing the mismatch between pin configurations(P.9 of datasheet) and schematics(P.25).I checked P.9 and P.25 roughly....
View ArticleRe: question about ADV7125 mininal input clock pulse width @ 165MHz input freq
and, we have got customer's input clock character(1) mode 1: input high pulse width 1.594ns, input low pulse width 2.697ns(2) mode 2: input high pulse width 2.730ns, input low pulse width 2.640ns(3)...
View ArticleADV7180 blue screen
Hi allI have some questions.I know that ADV7180 outputs a blue screen with no signal input.Does this part have the function of detecting no signal input expept a blue screen ?For example, can the...
View ArticleRe: question about ADV7125 mininal input clock pulse width @ 165MHz input freq
all this value is minial value, got by customer simulation.
View ArticleClik here to view.
Re: AD5933 Lower Limit of Frequency
Hi,Are you using the evaluation board of AD5933 through external control (in your case, Arduino)?Or your own custom board? If yes, can you provide your schematic? Can you also provide the following...
View ArticleRe: ad-fmcomms1-ebz programming FPGA
Good eveningThank u so much for your help sir..I'll try to make changes in test.c and check for output..I'll reply you incase of encountering some issues...thank u so much.
View ArticleRe: Testing the ADUM3220/3221
Hello, I'd be happy to troubleshoot your design with you, but it looks like the images haven't linked correctly. Can you please re-upload your images? There is a button in the forum editor that looks...
View ArticleRe: How to use an AD9959/PCBZ evaluation board ?
Hello, I have a new question.I said that I want to ouput frequencies around 80MHz plus 164MHz, this is false.I need to output 4 fréquencies around 80MHz synchronised with the master clock and quite no...
View Articleoperate on AD-FMCOMMS3-EBZ
I 'm a new comer,and i'm using AD-FMCOMMS3-EBZ on ML605(V-6), i want to know how to operate it .
View ArticleRe: Does ADAU1761 Support I2S input and I2S output, we want only use the DSP,...
Hi Allen, If each device in the system has it's own MCLK (master clock-in) source, there could be an issue with passing audio from the BT module through the external DAC if each of these are master I2S...
View ArticleProper termination of unused PLL LOOP FILTER pin on AD9910?
I'm providing an external clock to the AD9910 so I'm not using the internal PLL. What is the proper way to connect (terminate) the PLL LOOP FILTER pin on the AD9910 when the PLL is not being used? Note...
View ArticleClik here to view.
Re: operate on AD-FMCOMMS3-EBZ
i have done the following things :(1) I opened the HDL design. (2) I export the HDL design from Xilinx Platform Studio to SDK.(3) I created a new application project.(4) I copy the downloaded source...
View ArticleAD9910: Is 100 Ohm LVDS termination needed on SYNC_OUT?
I'm running the AD9910 standalone, so I am looping the LVDS SYNC_OUT signals to the SYNC_IN inputs. Does this require a 100 Ohm LVDS termination resistor? Cheers,David
View ArticleRe: AD8361 recommended FLTR capacitor in BPSK
Yes, a 0.1uF CFTLR would provide adequate noise averaging. By lowering the communication speed on the BPSK signal, only the phase content changes and not the amplitude or frequency, hence the value of...
View Article