Hi Vaibhav,
1. To understand the Tx and Rx chain, maybe you should start to read a little more about the device, the ad9361. After that you can try to understand the hdl part of the things, I would recommend this two link: ADI Reference Designs HDL User Guide [Analog Devices Wiki] and AD-FMCOMMS2-EBZ / AD-FMCOMMS3-EBZ / AD-FMCOMMS4-EBZ HDL / AD-FMCOMMS5-EBZ HDL Reference Design [Analog Devices Wiki]
The majority of the IP are Xilinx proprietary IP, so you could find more information using the DocNav software, which was installed with the Vivado. The very simplified tx/rx path looks as follows: DDR3 <-> DMA <-> AD9361 IP core <-> AD9361.
2. The role of the DDR is quite obvious, we need to move a lot of data from and/or to the device, and that data need to be stored somewhere. The role of the DMA is to move data between the DDR and the device. Because the ad9361 is a transceiver the design has two separate DMA for transmission and reception. Check the dac_init function in dac_core.c, this segment maybe the most important, where the DMA is set up to move data from memory to core. You can see the same thing, but now on the other direction, at the adc_capture() function in the adc_core.c.
I hope this will clarify a few things.
Thanks,
Istvan