Hello Kasbah,
I do not have an evaluation board handy to try this. I did look at the evaluation board documentation and schematics. It is interesting that there are provisions for tri-stating the CPLD for data and clocks but not for communication. The other interesting thing is that the schematic has the comm ports labeled as SPI ports when they are really I2C ports. But let's move on...
I think you should try disabling the CPLD altogether and holding it in reset. Usually all the pins are tri-stated in this condition so that should work. There are two pins on the CPLD that may help you do this. I looked for the datasheet of the CPLD and could not find it.
R48 is tied to ground and to the Enable pin on the CPLD
R49 is tied to 5V and to a pin named TRST on the CPLD. I will take a leap and say that pulling the TRST pin to ground will tri-state the part. The ENABLE pin to 5V may hold the part in reset. One of these should accomplish what you are trying to do.
Let me know how it goes.
Thanks,
Dave T