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Re: ADAU1761 Problems: PLL and Alias

Hello Philipp,Yes, setting the converters, I2S bus, and core (if used) to 0.5 x fs is the way to get 96K operation.  Hope your project goes well. Bob

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AD8317 operation at 10GHz & impedance matching

Hello, I am interested in using the AD8317 log amplifier at 10GHz.  The AD8317 is specified for operation up to 8GHz, but can be used up to 10GHz with a reduced dynamic range. The datasheet (page 15)...

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Re: Problem with ADV7619 consistently locking to an Apple IPAD.

Hi Stan, Do you have any other EVAL-ADV7619-7511 boards that you could test? It seems like your board is not functioning correctly. -Matt

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Re: ADIS16209 correct inclination angles under the arbitrarily changing force

Thanks!

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Re: ADuCM360 PGA gain-bandwidth

Thanks.  Only <= 100 Hz even at low gain?  It seems to work OK with PGA gain=2.

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Re: Problem with ADV7619 consistently locking to an Apple IPAD.

Matt, I have another development board but it requires U-boot to be loaded. I do not have an ICE. The development board locks correctly to the 804 generator but not to the IPAD. I will try my Galaxy...

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Save captured image on SDRAM - 0x2C fault

Hello.I am using ADZS-BF526-EZLITE and OV7670 cam. I am trying to capture an image using PPI port but i have a problem with saving it on SDRAM.I want to capture image with VGA resolution and matrix are...

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Re: ADXL345 output variation vs sample rate?

Thanks Neil. I believe your last response goes directly to the issue I am experiencing.  I was aware of the offset null procedure described in the app note you attached. I now understand that the...

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Re: Problem with ADV7619 consistently locking to an Apple IPAD.

Matt, Please answer the following question. Using the development board.  Monitoring the HSYNC pin with a Frequency Meter  When locked the H rate is 67434 Hz, source is a 804A signal generator at...

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Re: BPF Design using Filter Wizard

Note that the center frequency also should be the geometric mean of the passband cutoffs.   The geometric mean of your passband frequencies is:sqrt(100 * 3500) = 591Hz Since this is different than the...

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Re: Questions about data sheet of HMC6000LP711E

Hi Bridget, To perform a write, the data bit to be written should be set to the proper state prior to applying the clock leading edge, that's why the diagram shows the clock edge in the middle of the...

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AD5933 phase data issue

Hello,  I'm programming the AD5933 chip. I'm doing several tests now to validate the data that I get from the code that I wrote.For that I use the *default* values of the EVM board (start = 30kHz,...

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Re: AD8336 Output signal level

Hi Kris, Figure 5 in AN-934 is a special case that shows how to connect the AD8336 to accommodate an offset gain control voltage by using the floating control feature. If you simply need to evaluate...

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Re: Is AD9914 DAC Calibration necessary when using single device ?

If a DAC calibration has been omitted, the main indication is degradation in both phase noise or noise floor. That said, once a DAC calibration is performed, the device should perform over temperature...

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Re: Disabling CPLD on EVAL-ADAV803/EVAL-ADAV801

Hello Kasbah, I do not have an evaluation board handy to try this. I did look at the evaluation board documentation and schematics. It is interesting that there are provisions for tri-stating the CPLD...

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Re: S-Parameter of HMC928LP5E

I want to ask the same question. Thanks

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Re: Question about AD9269 input CLK jitter

Hi Wen, Thank you for using the AD9269. The AD9269 clock jitter requirements are based on your SNR requirements, and not on the AD9269 itself. Figure 55 in the AD9269 datasheet shows the relationship...

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ADuM1251 shows no reaction

Hello, in my project i'm working with an ADuM1251.Following picture shows my setup.The microcontroller is connected on PIN 2 and PIN 3. On PIN 6 and 7 four I²C Slave-Devices are connected.If i start my...

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Re: Questions about data sheet of HMC6000LP711E

For WRITE, A and C are aligned. Or we say that B and D are aligned.  The reason that the 1/2 clk cycle DATA is ahead than CLK is to make sure that data is ready on DATA line and wait for raising edges...

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Re: PCB considerations - Sigma ADAU1452

Thank you Craig.  After I posted this I realized that it was in the general DSP category and not the specific chip category but I couldn't figure out how to move it. 

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