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Re: Question about AD9269 input CLK jitter

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Hi Wen,

 

Thank you for using the AD9269.

 

The AD9269 clock jitter requirements are based on your SNR requirements, and not on the AD9269 itself.

 

Figure 55 in the AD9269 datasheet shows the relationship of Input Frequency (X-axis), SNR (Y-axis) and clock jitter (different curves). For a given input frequency and clock jitter, you can see how much SNR will be degraded.

 

At low input frequency, jitter does not affect SNR much. It will be about 77dBFS regardless of jitter. At high input frequency, there is a huge jitter effect. Below I've added some explanation to Figure 55 as an example:

AD9269_SNR_vs_Jitter_example.dib

So, from a jitter perspective, your clock source will "work" with the AD9269, but if the jitter is low enough depends on your SNR requirements.

 

Some other points to consider:

  • The jitter in your clock specification table is "cycle-to-cycle" jitter. This is not the type of jitter that is applicable here. The component of jitter that is relevant to SNR here is RMS random jitter.
  • The AD9269 has internal jitter that needs to be added to the jitter from the external clock source. Combining uncorrelated jitter sources needs to be done in a Root-Sum-Square fashion.
  • It looks like your clock source is a 3.3V or 5V device. The AD9269 is a 1.8V device, so you need to make sure you do not over-drive the clock inputs.

 

I wish you the best for your project. Please let me know if you need more information.

 

Thank you.

 

Doug


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