The ADV7511 is rated only to TMDS clock of 225MHz. 1920x1080@120 would require 297MHz. The 7619-7511 eval board was never designed to run at that rate.
The 7619 will handle 3G. I'd check the LLC DLL phase adjustment to make sure the FPGA input data is meeting the correct timing constraints. Run a schmoo plot of all the phase setting and pick the best one. See if that resolves the 7619 to FPGA link.