First of all, I am using ADV7181D, not ADV7181C. You are refering to table 10 of the 7181C, which is really table 11 on the 7181D.
Second. I understand the 12bit DDR timing of clocking on rising an falling edges shown in figure 5
Third. And this is perhaps my confusion: IF I set CPOP_SEL to 0100 mode (12 bit DDR) and set DDR_EN to 1, set PRIM_MODE to 0000 (SD-M) and VID_STD to 1010 (4x1 525i) to process 525i RGB SOG, what is the clock frequency at the LLC output pin?. The documentation is not very clear on the difference between sampling clocks, pixel clocks, LLC1 and LLC PIN. With these settings, what is the sampling frequency, pixel clock (13.5Mhz?), and the clock frequency at the LLC pin output?