Re: Problems in ADV212 register reading and writing
Hello David, Very sorry for my delay.The max current our 1.5v core can supply is 3A. Someone work with me tell me it may enough and let me don't worry that. We have checked the voltage of 1.5v is ok...
View ArticleRe: Kernel panic - not syncing: VFS: Unable to mount root fs
I've been trying but looks like something is wrong with the Flash on my bf518 board, before I can have any progress I would suggest you to use the build_jffs2_fs_kernel.exp scripts to make a build, see...
View ArticleRe: CN0287 accuracy analysis
Hello Suresha N S For this circuit, we assume customer doing the system calibration to cancel out all the linearity error. Besides that, the non-linearity error (drift, noise) would decide the final...
View ArticleRe: type of interface in dds ic ad9959 to generate a lfm signal
Hi David You're right, I misunderstood the 2 bit serial mode as an I2C interface. I apologize for that. ThanksLouijie
View ArticleRe: Can't run bfin_sport.ko driver. Why?
Excuse me.Full log from power start is attached.
View ArticleRe: AD7288 conversion data
Hi , I went through following discussion .http://ez.analog.com/message/44415#44415 AD7357 states clearly that it the data is from previous conversion but how do you know if it is from same conversion...
View ArticleRe: Problem in FMCOMMS-1 with xilinx KC705
Hi, I see it.Thank you. And about the problem with the DMA transfer,I will check it again and look forward to your reply. Thank you again. Yours,Pluto
View ArticleADUM3481BRSZ Safety and regulatory approvals
Dear What's time will upload below Safety and regulatory approvals of ADUM3481BRSZ on Web side?UL recognition: 3750 V rms for 1 minute per UL 1577CSA Component Acceptance Notice #5AVDE certificate of...
View ArticleSine Generator
Oliver Hi,I need two sine waveforms at 90Hz and at 33KHz. I get the 50% duty cycle square wave from a CPU.Do you think that 4 order LPF is not enough to attenuate the harmonics content?What is your...
View ArticleRe: True range of ADXL001-70
Hi GTBecker, This is possible. The typical measurment range of ADXL001-70 is +/-70. It is possible that some parts have a little wider measurment range. Thanks. BRNeil
View ArticleQuery about AD8375's Output Design
Hi, there I choose AD8375 because of It's IMP data only ( i.e., 2nd harmonic ). In evaluation board schematic I need some clarification, Below things are I observed from the evaluation schematic ,...
View ArticleRe: CN0224 Altium Designer
Hi Dani, I'll ask around but I think what is there is all we have. Dave
View ArticleRe: Sigmastudio not saving IIR table coefficients in index selectable filter
Hi Gertjan, I finally managed to see what you're seeing. I think the key is actually in using the arrow keys. When I use the drop-down window, I don't have problems, but when I scroll through the...
View ArticleRe: ADV7181D 12 bit RGB 4:4:4 DDR mode
From Table 10, 5th line down, Pixel port P19], the up arrow indicates that B[7] is valid on the rising edge of the clock, and the down arrow indicate R[3] is valid on the falling edge of the clock....
View ArticleRe: TS201S EZ Kit CPLD to communicate with an external A/D converter
Thanks for the support! Pedro Paulo.
View ArticleRe: what happens if I exceed the maximum f(core)?
Hi bowerymarc, Sorry that it took me a few days to get back to you. I don't think overclocking the device would damage the device in any way. Actually, I'm surprised that the PLL was even able to lock...
View ArticleNew Zynq release - 12Dec2013
Please check out the new Zynq release. http://wiki.analog.com/resources/tools-software/linux-software/zynq_images If you have any questions about it - let us know.-Robin
View ArticleRe: CN0224 Altium Designer
Hi Dave can you give it a try by exporting in p-cad ascii format. That way Altium might like it more. Unfortunately I don't have access to P-CAD. Best regards Dani
View ArticleRe: ADV7181D 12 bit RGB 4:4:4 DDR mode
First of all, I am using ADV7181D, not ADV7181C. You are refering to table 10 of the 7181C, which is really table 11 on the 7181D. Second. I understand the 12bit DDR timing of clocking on rising an...
View ArticleRe: IMAGEON FMC ADV7611
I have built the new kernel from revision 71915... in the imageon_zynq branch and I used revision 5brfb... of the HDL project, but I still have a slight issue. The /dev/video0 device is registered...
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