Re: Problem:i cannot get the right data from the ADIS16448 when it is waggled
SMPL_PRD's value is 0x0B01, SENS_AVG's is 0x0402.The ADIS16448 is an autonomous system that requires no user initialization. When it has a valid power supply, it initializes itself and starts...
View ArticleMinimum HSYNC frequency for AD9984A
We currently use an AD9985A in our product but will be coming out with a new design. Since the AD9985A is no longer recommended for new designs (even though it still seems to be in production and...
View ArticleRe: CN0303 Software Time Domain Data Capture Depth
Dear NevadaMarkCould you give the Labview Source of "CN0303: MEMS-Based Vibration Analyzer with Frequency Response Compensation" Thanks
View ArticleRe: ADV7401: can we modify the HS/VS synchronization signals if setting the...
Hi Xavier/Mick,Thanks for your answers. Yeah, we need to change the HS/VS begin/end positions when setting DEF_VAL_EN to 1. Can we? Best regards,Fancy
View ArticleQuestion about adv7511 aspect
Hello Could you tell me the diffreence between 0x56[3:0] and 0x56[5:4]?0x56[5:4]:picture aspect ratio.0x56[3:0]:active format aspect ratio.How should I do when I want to set a 4:3 or 16:9 output?Thanks !
View ArticleRe: ADV7511 snow noise
Hello Guenter ! I try to turn off the input video until the hdcp is authenticated.But it also has the snow screen.Our input is 480p bt656.I wait a long time to ensure the hdcp is authenticated and the...
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Adis16209 test issue
When i test ADIS16209， the Y-axis output was affected by X-axis inclination angle, 1、X-axis 0°，Y-axis rotate 0°\10°\20°\30° ，the output is right. 2、X-axis inclination 30°，Y-axis rotate...
View ArticleAD9361 Noise figure measurement
We are having AD-FMCOMMS3-EBZ (ad9361) evaluation board. For measuring the noise figure, we connected evaluation board to XILINX zynq FPGA board. In ADI IIO oscilloscope settings we provided: RF BW=...
View ArticleRe: I need Labview source code for EVALCED1Z+AD7606
Hi Ali. Sorry for the delayed response our team has just returned from annual leave.Would you like me to forward you on the source code for the CED board? And do you require FPGA code also? Regards,Rob
View ArticleRe: How to use configuration file ad-fmcomms3-ebz.cfg for AD-FMCOOMS3-EBZ borad
Hii ACozma ,May I know where I will get help how to port GNU RADIO on zeb board ?? And how to convert qpsk model to hdl coding?? And will you suggest any good way to proceed for making whole setup...
View ArticleFMCOMMS1: Using custom IP core to generate data
Hello larsc,I have a query.Instead of dma, I would like to use my custom ip to generate 64 bit data.At what clock should I generate this data?Should it be equal to fifo_rd_clk = 122.88 MHz?Thanks
View ArticleRe: Using Internal SRAM in BF538F
Hi, The li1040 error indicates that you have too much code to fit in the internal memory of the processor - by a significant margin, in fact, at 0xbd22 words (~48K). Two things you could try are...
View ArticleTMDS clock activity detection circuitry doesn't work when enable ADV7844 ADC...
Dear experts,It is said in ADV7844 hardware manual, TMDS clock detection circuitry is active and functional when the ADV7844 runs in simultaneous mode. According to the guidance, my customer enable...
View ArticleRe: How to use configuration file ad-fmcomms3-ebz.cfg for AD-FMCOOMS3-EBZ borad
And after porting the model in hdl coding form on zed board how to run that model through fmcomms card??
View ArticleRe: FMCOMMS1: Using custom IP core to generate data
Hi, I've branched this into a new discussion. The clock frequency depends on the configure sampling frequency of the AD9122. By using the fifo_rd_clk as the clock for your signal generator you'll...
View ArticleRe: CCES 1.1.0 "COM1 : Cannot open port COM1" problem
Hi, The CCES tools do not access the COM port. Can you check the Pre/Post Build options on the failing machine via Project: Project Properties: C/C++ Build: Settings: Build Steps. Are you invoking any...
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Re: Zero init sections at boot time vs run-time
Hi, We provide a "memory initializer" utility which is part of the CCES tools. For documentaiton, take a look at Help > Contents > CrossCore Embedded Studio 1.1.0 > Linker and Utilities Manual...
View ArticleRe: ADuC7061 DAC
As specified per page 8 of the data-sheet for 14-Bit resolution (in 16-Bit Mode) the DNL is +/- 1 LSB.Best results to get with the reference < AVDD - i.e. using internal Vref.
View ArticleQueries about Hittite X-band 500W PA KHPA-0811W
Hi, In its datasheet, it is said that DDH package is 2.3" * 2.5", and what's the height?The efficiency is 22.5%, what is the testing condition? how about the testing frequency? Could you please help...
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