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Issue on IRMS using ADE7953 when the value exceeded the full range

Hello, On my project, I use ADE7953 to read IRMS and VRMS value. Upon the data sheet, "with full-scale inputs on current channel A and B, the expected reading on the IRMA and IRMSB register is 9032007d...

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Re: ADV7441A with EIA-RS-170

Yes, unfortunately I need industrial grade (and I cannot use BGA for this project). 

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Re: AD9910 Eval Board External Control

I've been having trouble locating AD's firmware for the USB chip on the AD9959 evaluation board, as in this topic: http://ez.analog.com/message/138861 .  Any chance one of you knows how I could get my...

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Re: AD9834

Hi baban79, If you are not aware, these forums are visible to everyone on the internet.  If you want to remove your contact information from your messages, there is an edit button in the lower left of...

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Re: AD9834

Hi baban79, The AD8302 requires two input signals and outputs the magnitude and phase difference between them.  You would not be able to test it with a single AD9834 evaluation board and use the part...

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Re: AD9834

Hi baban79, I cannot make this discussion private.  The most I can do is delete it and we can move this discussion back to email.  By the way, the person responding to you above is Miguel.  He's the go...

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AD-FMCJESDADC1-EBZ reference design not working with ZC706?

I have a ZC706 and AD-FMCJESDADC1-EBZ. I am trying to get the reference design located here http://wiki.analog.com/resources/fpga/xilinx/fmc/ad-fmcjesdadc1-ebz up and running. I follow the provided...

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Re: DTDs for 1920x1080p in Advantive EEdit2.

DTD's don't appear to be required as long as the VIC in the CEA block has the right VIC enabled

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Re: ADV7612 reset: hardware, software or both?

I confirmed that setting the MAIN_RESET bit and asserting the RESET pin have the same effect. I would suggest that you wait 5 ms after either type of reset. -Matt

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Re: Power UP/Down sequence of ADV7390

The real problem on chips with dual power rails if current flows from one rail to another rail on the chips caused by having the wrong voltages for too long, the current flow through the chip will heat...

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AVES3 - ADV7850 eval board folder

Hello,I'm in need of the AVES3 folder for the Advantiv™ EVAL-ADV7850EBZ Video Evaluation Board.thanks!regards,KevinL

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Need suggestion for CCD front end

I received the following inquiry from a customer.  Please provide suggestions: We are considering using a Sony ILX554B, Sony ILX511B, or Hamamatsu S11639 linear monochrome CCD.  Do you have analog...

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AD-FMCOMMS3 Zynq ADC input level

I'm uning the Zynq platform with an AD-FMCCOMMS3-EBZ board and I hve a question about one of its settings in its normal operating mode. What is the default setting for the ADC headroom? What is the...

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UART over SPORT on BF52x example?

Hello All, Anyone have working example code of the UART protocol over the SPORT interface on the BF52x? Written in C?I have the TX side working correctly but am running into issues on the RX side. Any...

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Re: High pass filter issue for sigma3.9 version.

     Hello Paul,      Your two screenshots appear identical (both from SigmaStudio 3.9), so I'm not sure if you're referring to the coefficient calculations, their location in parameter memory, or a...

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Re: Before buying the AD-FMCOMMS1-EBZ and KC705/VC707

Kurtul: We don't support that sort of environment. You might be better off using something like the:http://epiqsolutions.com/sidekiq/and then something...

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Re: ADI IIO Oscilloscope installation problem.

Raveendra:  There is no issue to solve. You are asking a question where the answer is do not do that.  The current version of IIO scope is for the Zynq target - not the host. -Robin

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Re: AD-FMCOMMS3-EB_AD7291BCPZ ADC usgae

It's available (unscaled) in the IIO scope, which you can run on the Zynq board directly. -Robin

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Re: AD-FMCJESDADC1-EBZ reference design not working with ZC706?

If you have a 706, can you try the SD image that we have with that card? http://wiki.analog.com/resources/tools-software/linux-software/zynq_images -Robin

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Re: Missing files in latest FPGA release?

Oguzhan:  The errors are expected unless you follow the directions that Lars and Adrian have provided (twice).  Did you follow the directions?  -Robin

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