Hi,
Now, I found that The Ext. 16-bit SRAM can be read and writen 16-bit data, but can not be read and writen 32-bit data, such as int data type. I think this cause the code can not run in ext. SRAM.
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Re: Using SRAM for code with ADSP-BF518
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Re: AD9361 Initialization error in FMCOMMS5 with ZC702
Marcin,
My problem did occur on the config.h file.My current display is as follows.Good worship you！In addition to this list of failed entries, I also want to ask, I use fmcomms5. There are two 9361 needs to be initialized, and now I have only one 9361 initialization, how do I initialize the other one?vMay I trouble you for guidance again?Thank you very much for taking the time to answer for me.
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Re: Does AD9249-65EBZ comes with FMC ?
Hey Doug
As i can see in the user guide, this evaluation board doesnt have a FMC ?
https://media.digikey.com/pdf/Data%20Sheets/Analog%20Devices%20PDFs/AD9249-65EBZ_UG_Web.pdf
Could you provide me a website link where i can order the same board with FMC connector ?
Best Regards
Rizwan
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Re: AD9361 Initialization error in FMCOMMS5 with ZC702
DragosB，
Thank you very much for your reply.My question is indeed that the file in config.h has not been modified.I have changed it.
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Re: AD9361 Initialization error in FMCOMMS5 with ZC702
Liuj,
I am happy that I could help you. I guess that now both of chips are running, I can recognize it on your picture. You have few comands to i.e. adjust sampling frequency, LO frequency etc. for TX and the same for RX. Send some signals from your carrier and try to see them on spectrum analyzer.
Regards,
Marcin
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Re: AD9364 products Tx single-carrier with a lot of clutter and low transmitting power.
It looks like you are saturating the TX path. What is the power of the input 1MHz tone that you are giving to the Tx. Try reducing the 'TX CW amplitude' to 1024 codes and see.
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Re: ADG749: SPICE Noise Analysis
Hi BR,
The ADG749 spice model does not have a noise parameter included in the model.
Can you share your application, why are you looking at this behavior?
Best Regards,
May
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AD9375 LO PLL and QEC settling time
Hi,
We are planning to use AD9375 for our frequency hopping application where we may requires minimum 2000 Hops/sec.
Where we require Receiver and Transmitter LO frequency settling time is <5uS.
Since the internal Architecture is based on PLL based, We don't think the PLL settling time is better than 50uS which may not meet our application requirement.
So we are planning to use our external LO signal to AD9375 with fast switching Synthesizer.
1) What is the internal PLL settling time?
2) During frequency hopping what will be receiver and Transmitter QEC settling time? This is required for us to finalize the AD9375 for our application requirement. If QEC settling time is more than 10uS then we may not use QEC for our application. In this case of QEC disabled what will be image rejection specification of AD9375?
3) How to switch the internal LO to external LO what is the switching time?
Regards,
Sugumar K
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Re: RX DMAC synchronisation
Hi Lars,
i have connected now a counter to fifo_rd_underflow on the TX dmac and it increments sometimes, so I have underflows during cyclic playback.
In the picture below, the blue line is the loopback signal from tx dmac fifo_rd_dout[15:0] connected to s_axis_data[15:0] of the rx dmac through the ddc, which in this example only stores each 32th sample in a 2048 words buffer, which ensures that the rx dmac receives full frames and during overflow skip a number of full frames. TX dmac is running a buffer with size 65536 with incrementing values in cyclic mode.
The green line is the difference between two samples of the blue signal.
The red line is the 16 bit counter in the PL which running on the 286.72MHz clock, connected to s_axis_data[31:16] of the rx dmac. On this signal we do not have such jumps.
Cosidering bandwidth, the TX part of the design is the same as in fmcomms1 with ZED board, with an other clock generator and a Zynq 7030-3 (Enclustra ZX5 module). The AD9122 interface clock is running with 286.72MHz, 16Bit DDR, 9.16GBit/s. Tx DMAC is connected to HP2 with 64Bit, 200MHz fclk1, 12.8GBit/s. So the 10% margin is met. The TX DMAC has its own HP port. 1GB DDR3L Ram of the Enclustra board is running with a 533MHz clock, 32bit, 34.1GBit/s.
How can I avoid TX underflows?
Thanks!
Andreas
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Re: ADuM4223
Thank you for quick and detailed response!
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Re: AD9129-CBLTX-EBZ ADF4351 Loses Lock
Hello CAugusta,
the root cause has been identified, the power supply that we were using for the 5V had insufficient output current capabilities for the board. After switching to a more powerful supply the board works as expected.
Take care,
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Re: Eval board AD9172 as DDS system with external UPDATE
Hi Expjtt,
You can connect the AD9172 EVB, which is FMC-complient, to either the ADS7 or the ADS8 FPGA evaluation platforms.
However for DDS mode there is no need for an FPGA, and the DC reference to set the NCO output level can be generated on-chip. You can use the EVB standalone, and configure it using the ACE software, which is available to download on our website. Just make sure to install the correct plug in.
The AD9172 SPI has an upper limit of 80MHz, which speeds up FTW updates. Also SPI can be configured to auto-increment the address so only the data payload needs to be clocked in - this is convenient if updating a 48bit FTW for example, spread across 8bit data registers with sequential addresses. each NCO phase and amplitude can be controlled independently. Note that the amplitude register sets I and Q separately, so the full scale would be 3dB lower than the combined IQ full scale.
In terms of FPGA board sync, if needed, the AD9172 EVB has an HMC7044 onboard which can generate an FPGA ref clk (lanerate/40), a DAC ref clk, and SYSREF if subclass1. Alternatively you can provide the two required ref clk's externally from sources locked to a common 10MHz.
AD9171/AD9172/AD9173 Evaluation Board [Analog Devices Wiki]
I hope this helps.
Best Regards,
Arik
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ADUM6403 outputting noisy pulses instead of intended signal
I am using an ADUM6403 isolator to provide power and communication across an isolation barrier, with 5V VDD and 3.3V Viso. I'm sending a 4800-baud RS232 signal from the primary to the isolated side using channel A, but I'm not able to observe the same signal on the isolated side. The other three channels from the isolated side back to the primary side appear to function properly. The output of the isolator feeds a digital input pin on an IC, with very high input impedance.
The isolator is decoupled with 1 uF || 0.1 uF capacitors on both sides of the isolation barrier. The ground pins on each side of the barrier are bonded to each other under the package:
The images below show logic analyzer captures (12MSPS) of the primary and isolated sides (I've connected the two grounds to allow the analyzer to capture both sides, but the signal appears the same way whether or not the grounds are tied together). Channel 0 shows the isolator's output (pin 14), while channel 1 shows the input to the isolator (pin 3). The images below feature a 510-ohm pulldown resistor on the isolator's output, and indicate two different timescales of the same capture. I currently don't have access to an oscilloscope due to a snowstorm in my area but I'm planning to attempt to scope the affected signals tomorrow if able.
The following image shows the same setup, but with the pulldown resistor removed.
I would appreciate it if anyone had insight as to what might cause this issue, or any other troubleshooting steps/measurements that I could take.
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Re: About LTC7000
Hi
Could you provide us with up to date schematic of your prototype hardware? Please check RUN pin. Is it connected to VIN? Do NOT leave this pin floating. Check OVLO pin as well. Is this pin connected to the resistor divider? Do NOT leave this pin floating.
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Re: AD9173 JESD Modes question and mapping I/Q Data to serial streams
Hi,
What you are looking for is a "dual link" mode, where each link feeds DAC0 and DAC1 respectively with L=4. As for JESD204B modes supported by the AD9173, you can refer to Table 13 in the datasheet, reposted below:
There is another table which describes which JESD204B parameters to use. M=4 if you are using two I/Q DACs (which you will have to since interp=24x).
In terms of mapping, in dual-link mode, each link would carry IQ data for its respective DAC. The data split between the 4 lanes depends on the relation between the various clocks. M0 would be, e.g., the I stream, and M1 would be the Q stream for that particular link. The mapping is described in yet another table, as you had mentioned.
Consider the built-in PRBS tests, and the Repeated CGS and ILAS test as means to confirm the data is packed and clocked properly. You are on the right track!
You may also consider purchasing the ADS7, which may help with comparisons against a known working FPGA platform, and make sure the DAC is configured correctly.
Best Regards,
Arik
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Re: Bounary Scan with ADSP-SC58x and ADSP-21584
I was able to see with a logic analyzer that only some of the boundary scan register was shifting out on TDO. Boundary Scan equipment vendor, "JTAG Technologies" was able to replicate this, too. They saw by the BSDL that data seemed to be blocked about where the PCIe interface pins were. They suspected the unused PCIe section (not enabled on the SC587, only SC589) needed to be powered up for boundary scan to work, even though ADI's data sheet said to tie VDD_PCIE_* to ground if unused. Relayed this suspicion to ADI, who confirmed an error in the data sheet.
Need to spin another prototype rev to confirm this.
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Re: AD9694 Losing Sync & Real Data Output Only?
I'm still having this issue; has anyone working with the AD9694 (or any JESD data converter) seen something similar?
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Re: AD9173 JESD Modes question and mapping I/Q Data to serial streams
Hello Arik,
Thank you! That was the missing link (pun intended). To summarize your response: Table 13 describes the DAC operation and the corresponding modes are mapped in that table which correspond to later tables which determine the mapping.
Just to make sure I understand this correctly, I think my application would be mode 3 dual link. We would code the interpolation as 3x/8x for channel and main interp for each link. Link 0 contains the DAC0 I and Q data as M0 and M1, Link 1 contains DAC1 I and Q data as M0 M1 on link 1... so to code it a bit more succinctly, let Lx be the lane number and "<=" means "is assigned" or "gets":
DAC0 I <= L0M0
DAC0 Q <= L0M1
DAC1 I <= L1M0
DAC1 Q <= L1M1
Now the next question is: from figure 66, would I have to map the physical lanes I use to the logical lanes outlined in this figure to make sure the data gets to the right place?
So, if I'm using Physical lanes 0-3 for these links (on the PCB), I would map them as follows:
LANE MAPPING:
Logical Lane 0 <= Physical Lane 0 (L0M0 or DAC0 I)
Logical Lane 1 <= Physical Lane 1 (L0M1 or DAC0 Q)
Logical Lane 4 <= Physical Lane 2 (L1M0 or DAC1 I)
Logical Lane 5 <= Physical Lane 3 (L1M1 or DAC1 Q)
(I know how to modify the crossbar over spi and map physical to logical on this device, just asking to confirm my reasoning).
If that's correct, if anyone from analog devices is monitoring this, please feel free to use this as an "example setup" in the data sheet. QED would be more than willing to provide additional samples to document this for everyone's benefit!
If what I understood is accurate, then thank you very much Arik, you've been an immense help!
Bonus Round:
Just out of curiosity (bonus round), if we were to choose Mode 4 Single Link from table 13 with the 3x/8x configuration and I mapped the lanes as above (LANE MAPPING), would the data mapping then read:
DAC0 I <= L0M0 (logical lane 0)
DAC0 Q <= L0M1 (Logical lane 1)
DAC1 I <= L0M2 (Logical Lane 4)
DAC1 Q <= L0M3 (Logical Lane 5)
or is the fact that this mode has 2 channels per DAC (from table 13) and we are using single link, thus we are "limited" to map the lanes in a way such that I and Q data go to DAC0 only. i.e. if we want to do what we want to do, we have to use 2 links.
If you don't know, or this is un-orthodox, then no worries, I can always test it out and post the result here
Thanks again!
Sincerely,
Phil
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Re: AD9642 Input Offset versus Correction Range
Hi Robert,
No, I would not expect the DC offset correction to have any adverse affect on the input signal in this case. As I've stated the correction circuitry is designed to correct the internal DC offset of the ADC and not affect the external stimulus applied to the ADC inputs.
Best regards,
Jonathan
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Re: ADV7511 HDCP ISSUE
Hi,
I believe that software driver would handle the HDCP handling and it is recommended to use our software driver.
Figure 26 shows HDCP software handling from Programming guide explains HDCP software implementation.
The customer should responsible for HDCP link integrity across the system per HDCP license agreements, Can you
Please specify your ADV7511 part type?
Have you verified this with reference script?
We have several evaluation boards which contain ADV7511 and the source code for the software drivers can be downloaded. Evaluation boards are like EVAL-ADV7842-7511, EVAL-ADV7619-7511, EVAL-ADV7612-7511 etc.
For the evaluation board ADV7619_7511 the software driver download option is available at Advantiv™ EVAL-ADV7619-7511 Video Evaluation Board.
Thanks,
Poornima
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