Hi felipe.murcia,
Thank you for your questions. Please see my responses inline.
1- From the datasheet it is said that in active mode the microprocessor achieves 30uA/MHz, which are the conditions of these specification? does it include peripheral, IO and other internal block consumption or just the core and the memory?
[NK: The specification of 30μA/MHz in case of ADuCM302x, corresponds to the typical dynamic current consumption in active power mode. The specification is for VBAT = 3.0V, Tj = 25°C, prime number generation code executing from flash with cache enabled. The internal buck converter is enabled for better power efficiency. PCLK is disabled and no peripherals or IO, are active.]
2- User guide UG1091 in the power optimization section includes some figures of current again the figures mention that a prime number calculation is being run, I'm assuming this corresponds to a case where no peripheral or IO activity is taking place, would that be a correct assumption? Does it still include possible leakage of the IO?
[NK: UG-1091 provides guidelines on power optimization for the ADuCM302x and is useful in identifying factors that can impact power consumption and which can be tuned depending on the application requirements. You are right in your assumption, it is safe to assume that no IO activity is taking place and that no peripherals are active in the example scenarios used, unless stated otherwise.]
3- Are there any other test results that could help in a real world estimation of the consumption of the micro-controller, where a set of peripherals, IO operations and so forth are active? Would it be possible to know how the power domains are distributed to estimate the consumption of each internal block?
[NK: Please look at 'ULPMark-Peripheral Profile' that EEMBC have rolled out (EEMBC web page). We plan to update with our scores for this benchmark in the next two months. An image on the EEMBC web page provides details on the various peripheral profiles used to benchmark. Please review the same and provide your feedback on whether such a score in general, or energy consumption for any of the individual profiles in particular might be useful for you.]
4- When active does the buck converter directly power any internal blocks besides the LDO? which ones? Is there any way in which the LDO is inactive while the buck converter is active?
[NK: Please refer below for a high level concept figure showing the internal power architecture in ADuCM302x.
Note that whether the buck is enabled or bypassed, the internal LDO is always in the power path. This is because the 1.2V supply required by the Arm Cortex core and the memory blocks, is always derived using the LDO. This does not take away from the fact, that enabling the internal buck, would improve MCU power efficiency - particularly at VBAT voltages higher than 2.5V.]
Best Regards,
Narsimh
