Hi,
Please let us know whether you have followed the scripts from design support files and have written all register writes. If so, please provide which specific script you have used from design support files, also provide the register dumps for analysis?
We recommend customer to use our evaluation board and software driver as reference and this would be helpful for them to debug the issues that related to your hardware or software.
Best Regards,
Jeyasudha.M
Hi,
It seems your frequency plan is similar to the Board B on our evaluation board. The board B configuration is designed for the frequency below.
You may need to tweak the matching network if frequency plan is different from above.
The nominal LO power needed for this frequency is 6dBm. The performance will be degraded if power is not high enough, e.g. conversion loss as below
If you are using ADF4360, I believe a buffer amplifier is needed.
Regards.
Hi KarimEI,
Can you Zoom in on the screenshot on the 1st picture, also I'd like to ask additional information on how you use the part,like if you can your schematic, input configuration, whats your input voltage and reference voltage.
regards,
LLoben
Hi,
The internal PLLVCO of the HMC1197 is based on the HMC835 design and it only supports 'Open' mode SPI interface. You might also find the following link helpful:
https://ez.analog.com/message/219987?commentID=219987#comment-219987
Regards,
Sefa
I am glad that this I helps. Not sure what "core clocking" means, or why it matters in your application. Happy to see what we can find out, if you can help me better understand the definition and need a little better.
If the output is shorted to ground the maximum current will be 15mA. The part might get hot, but it will not damage the part.
Hello b_rad,
Thank you for contacting us here in engineering zone.
As you discussed there may be two different influences here for the larger emissions with the cable attached. How much pass margin do you require on EN60945?
1. The cable may be loading the RS485 and CAN devices and hence drawing more current from the isoPower devices hence increasing the emissions.
2. The cable may be acting like an antenna and providing an efficient antenna for the 360 MHz harmonic.
Can you provide any information on the cable you are using? Is there resistive loads (120 Ohms or other) on the RS485/CAN bus output pins? What data rates are you operating at? These parameters will help determine the expected emissions. Is the PCB in a metal enclosure? Please contact me directly at james.scanlon@analog.com if you wish.
To answer your questions in relation to AN-1349 and its applicability to the ADM3053E:
1. If it is vias for the stitching cap the vias should be placed as close as possible to PIN 11 and to PIN 14. The GND2 (isolated) layer and the VISOUT out layer (secondary side PCB layers) should not be connected to Pins 11/14/12. These pins should only be connected to the secondary side PCB layers through the ferrite beads as shown in figure 1 in AN-1349. This is also shown in figure 18. For each of the isoPower devices do you have a separate stitching capacitor or one full stitching capacitor the length of the board that all devices are connected to?
2. In order to achieve better emission data it is best to have minimum copper on the secondary side. However this is not always possible as many designs require planes for additional circuitry on the secondary side. The reference boards in that application note have secondary planes as this is often required. It is recommended tho for better results to remove as much copper (planes) as possible for better results.
To answer your questions to the ADuM5401 and AN-0971:
1. As described above the vias for the planes should be on the opposite side of the Ferrites to the ADuM5401. Again for this device pins 9 and 15 should only be connected to the secondary side GND2 plane through a Ferrite. Pins 9 and 15 on the ADuM5401 can be connected together similar to pins 14 and 11 on the ADM3053. Pin 16 on the ADuM5401 should only be connected though a ferrite to the VISO Plane. Also connect Vsel to either VISO or GNDiso on the ADuM5410 side of the ferrites.
2. Yes the discrete capacitor should be placed as close as possible to pins 8 and 9. are you also using a stitching capacitor here?
3. Yes better results are achieved with minimal copper on the secondary (isolated) side.
By following the applications notes mentioned and by implementing the points above the with the proper selection of ferrites this should limit the 360 and 1G signals from the isolated planes and hence reduce the emissions when the cable is attached. What ferrites are you using? The stitching and high voltage capacitor should provide a low impedance return path for the 360 CM noise. Please also refer to user guide UG-044 pages 4 and 5 for layout recommendations for the stitching capacitor and ferrite placement and PCB cutouts.
If you would like to provide images of your previous design/layout and your new design and layout I can review it to ensure all recommended layout guidelines are present.
Can you provide and image of your test set-up. Is the issue horizontal or vertical emissions?
Please contact me directly with any further questions and responses if you prefer.
Regards,
James
i had ran this command and I got the following output:
Library version: 0.10 (git tag: 11b871b)
Compiled with backends: xml ip usb serial
Available contexts:
0: 0456:b673 (Analog Devices Inc. PlutoSDR (ADALM-PLUTO)), serial=104473222a8700100b0013006cb1d51124 [usb:2.2.5]
but the issue is that matlab during hardware setup can't find radioID and this Serial nnumber
I cannot get a list mode or array mode memory DMA to complete using either fast stream 2 or 3. Only the single DMA block function adi_mdma_Copy1D() completes using fast streams 2 or 3.
I tried the CCES example project "Memory DMA Copy Array Mode (SC589 SHARC)" which uses adi_mdma_Copy1Darray() and it works fine on streams 0 and 1 but hangs here using fast streams 2 or 3:
while ((bMemCopyInProgress) && (TimeOutCount))
{
eResult = adi_mdma_IsCopyInProgress (hMemDmaStream, &bMemCopyInProgress);
if (eResult != ADI_DMA_SUCCESS) {
DBG_MSG("Failed to query status of Memory DMA copy, Error Code: 0x%08X\n", eResult);
break;
}
TimeOutCount--;
}
I used these setting for stream 2:
// Make MDMA2 Destination to generate secure transactions
if(adi_spu_EnableMasterSecure(hSpu, 140, true) != ADI_SPU_SUCCESS) {
DBG_MSG("Failed to enable Master secure for MDMA 2 Destination\n");
eResult = ADI_DMA_FAILURE;
}
eResult = adi_mdma_Open (2, &MemDmaStreamMem[0], &hMemDmaStream, &hSrcDmaChannel, &hDestDmaChannel, NULL, NULL);
if (eResult != ADI_DMA_SUCCESS) {
DBG_MSG("Failed to open MDMA stream, Error Code: 0x%08X\n", eResult);
}
I also tried the ADI project "Descriptor_Based_MDMA_Core1" and it works fine on stream 0 but hangs at WAIT_FOR_DMADONE(40) for stream 2.
I used these setting for stream 2:
//Enable MDMA2 stream as secure master
*pREG_SPU0_SECUREP140 = BITM_SPU_SECUREP_MSEC;
*pREG_DMA39_CFG=SRC_DMA_CFG;
*pREG_DMA39_DSCPTR_NXT=(int)SrcTCB1|0x28000000;
*pREG_DMA40_CFG=DST_DMA_CFG;
*pREG_DMA40_DSCPTR_NXT=(int)DestTCB1|0x28000000;
//Wait till the second work unit is complete
WAIT_FOR_DMADONE(40); // destination DMA channel
Please explain how to get memory DMA to complete using array mode or descriptor mode using either fast stream 2 or 3.
Thank you
You can buy these on Digikey. Remember that you also need to purchase a carrier module.
Hi all,
Just looking for someone to point me in the correct direction to find details about using these interfaces (I2C, SPI, PWM) on the ADRV1CRR-BOB.
Thanks so much!
Jacob Hempel
I've received EVAL-ADV7612-7511. Why is the EDID 256 bytes. Isn't EDID 128 Bytes.
Is there an EDID tool that can show what each EDID byte means. I have EEDIT and the output of this tool is 128 bytes.
The system I'm working with requires me to modify the monitor name in the EDID file to our own before HDMI output is enabled.
Also, is there a way to GUI display which controls all the register bits with the Advantiv software.
Thanks.
EDID can be multiple blocks of 128 bytes. Common EDIDs are 256 bytes or 2 blocks. The first block being the legacy VESA block and the 2nd block the CEA block. Check out Advantiv™ EDID Editor
For register controls check out
Advantiv™ Video Evaluation Software (AVESBlue)
Folder can be found
Hi Mark,
I know your busy but is there any progress on this?
Thanks,
Steve
Hi KoRba,
The scope of this question is large. I don't know what to do with it.
If you have a specific question regarding the ADA2200, let me know.
Best,
Brian
Correction: this one is about input analogue pins. Internally they seem to have 1M resistor (at least from the spec). What's the point of 270R?
Also different pins have different pull up/down resistors in evaluation schematics (some 10k some 100k some none at all). If I didn't have an evaluation schematics where can I find information on how to properly route everything from data sheet?
I am using mine in hardware mode. Is pull up resistor of 10k okay for between VDRIVE and pin for all configuration pins (!WR/BURST for instance has 100k resistor, SER/!PAR has 10k resistor)?
Have you installed DPGDownlaoder?
Sorry I do not have Spectrum analyzer. Not right now.
Is there any way I could verify if the code is working or not. I tried reading back from the ADC DDR BASEADDR after adc_capture() but i could not compare it with the values of sin_lut()
I made sure that something is being written because when i read values from ADC DDR BASEADDR before running adc_capture() all values are like 0xff00ff00.
I modified the sin_lut() by changing all values to constant 0 in order to check if I get some similar effect but when I read from ADC DDR BASEADDR, the data is still random. Please let me know some way which can help me verify that everything is working fine.
I have a very little knowledge of RF and your help will be highly appreciated
Regards
Jacob,
What are you looking for?
The break out board particularly doesn't care (other than the fact that these are the device interfaces)--
Example, the i2c devices must be connected to an i2c master.
In our case, it is the Xilinx axi-i2c core in the SOM.
Also SPI/PWM doesn't really matter much (no devices on the break out board carrier).
The only carrier specific I can think of is the FMC (AD9517).
Hi,
Yes you are correct, when selecting multiple channels in continuous conversion mode, the ADC continuously converting through the enabled channels, selecting each channel and performing one conversion on the channel. You can read the present conversion while the next channel is converting. One possible cause could be you are reading the present conversion several times before the end of the next channel conversion. Can you confirm this? May I know if you are polling the RDY upon reading the conversions? Are you also including the status register upon reading the data register to see what channel corresponds to your conversion reading?
Thanks,
Jellenie