Hi,
Thanks for your help! Indeed, all clocks are derived from the soundcard. I use a CPLD as "glue logic". The soundcard's MCLK = 512*fs, is divided by 2 in the CPLD to get the BCLK (256*fs) for the 8 channel TDM DAC.
I've implemented 100 ohm series resistors in the clock- and datalines from the soundcard to the CPLD and from the CPLD to the TDM DAC. I'm planning to test with these series resistors in the clock- and datalines from CPLS to ADAU1701 as well. Takes some patience and steady hand to do that...
All ideas are welcome :-)
