Thank you for your reply!
I used a IBUFDS to change the data_clk_n and data_clk_p to the CLK signal.
Then connect the CLK signal to an ILA as the probe input to get the wave profile.
The clk which the ILA running at is a FPGA 250MHz clk.
I think the result should be like the first picture.
But where I point in the second picture is someting wrong.
Thank you.