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Re: EVAL-ADV7612-7511P testing by AVES3

Dave: when 0x9e[4]=0b1,PLL was locked.0c42[6]=0b1,HPD is high.the value set of registers  would be restored to 0 soon itself,why?such as 0x17,0x17,0x48,0xaf,0x35,0x36...

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Re: Video decoder and Video encoder

In Latin "errare humanum est"-  Back to our business. Based on "For YCbCr over  an 16-bit bus the clock rate will be 13.5MHz.  8-bit bus the clock rate will be 27MHz" we will need encoder and decoder...

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Re: HMC460LC5 biasing

Hi Tim, RF I/O pins are DC coupled; hence external DC block capacitors are required, if the DC offset voltage level is not 0 volt on your application. Best,Kagan

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Re: ADM2483 with isolated power supply

Hi John, Thanks for the feedback. Could you take a look at the micro ATXMEGA16A4 programming? The U5 ADM2483 is connected to pin PC2 of the ATXMEGA16A4.Your setup and problem description is pointing...

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Re: ADA4870 high output current op amp

Hi Anna In the pspice model of ADA4870 , just some of pins of  IC is considered as :* Node Assignments*  Non-Inverting Input                      : 100*                 Inverting Input                :...

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Re: Acquisation time Q

not quite because a different board with the only difference being a 1MSPS instead of 2, and the acquisation time is 800ns this time. with clock,SCLK Freq all staying the same, just a different throughput

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AD7606 NIOS II Error

Hello (Sorry my English) I get an AD7606 Eval CED1Z board for my project. I have an error on NIOS II software. You can see the Error on the figures. Can you helpto solve this problem. Ali Akay

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Re: Kernel 3.17 locks up when using display VDMA

Hm, right, I fixed this in upstream, but apparently the patches didn't trickle back down into Xilinx kernel. I've cherry-picked the fixes from upstream, things should work now again. - Lars

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adv7612 i2c isn't acked, but crystal of 28.636Mhz is working

Hi:   we are using adv7612 to receive 720p video from top-set box, but the i2c access to adv7612 doesn't work, the detail is as below:1. we set the VS/FIELD/ALSB pin as being floating, so the IOMAP of...

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Re: AD 9361 on BSC9131 of Freescale - queries

Hi, The driver and documentation you are reefing to is provided by Freescale.You should ask for support there. We only support this AD9361 Linux...

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Re: ZC706 ad9680_eval project

Thanks for the reply. I also have that board and successfully built that project, but this is for a different AD9680 eval board which has an FMC pinout compatible with the ad9680_eval zc706 project. Do...

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Re: ZC706 ad9680_eval project

For reference, the part number of the eval board I would like to use with this project is 9680EE03C.

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Can I program a RLS filter using SigmaDsp on a ADAU1401A (SigmaDSP 28-/56-Bit...

Hello all,  I want to implement a RLS filter using the program SigmaDSP on a ADAU1401A. Is this possible? I don't find the right way to do it.  Thank you in advance

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Phase Detector for 12nSec square signals chip

Inquiry Description: Hi All I'm looking inside the AD product in order to choise the right chip to realize a quite Low Frequency phase detector. My goal is keep in phase two pulsed signals (Pulse...

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Re: ZC706 ad9680_eval project

Hi, this is the same board as AD9680-1000EBZ. It is just the engineering evaluation board. FMC connections are identical to the AD9680-1000EBZ. Umesh

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Re: AD-FMCOMMS3-EBZ HIL example: QPSK modulation with raised cosine filter

The issue related to the constellation switching between good and bad states is due the lack of phase recovery in the QPSK model. Since the receive RRC has a decimation of 4 the easiest way to...

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Re: ZC706 ad9680_eval project

Thanks very much for the clarification, Umesh.  I took a look through the files and they don't seem too far off from working, but I wanted to check to see if anyone at ADI already has a version of the...

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Re: Regarding AD9361 Calibrations

have you verified the digital interface for the receiver path? if not i think there is a digital loopback option available, try it to validate your interface if you are using chipscope to collect...

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Re: ADF4108 Power Supply

Hi Joe,The specifications in Table 1 are guaranteed over the supply range at the top of the page ( AVDD=DVDD=3.3+/-2%)  ,unless otherwise noted in Table 1. Regards,Brigid.

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Re: calculator for hittite pll products

Hittite's online PLL design tool that used to be located under 'Product Support on the home page is no longer available. However, the MatLab based, Hittite PLL Design tool can still be downloaded from...

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