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About Digital data output

March 19, 2018, 5:29 am
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Hi, I'm using AD9613 with HSC-ADC-EVALCZ board programming with labview.

 

I have questions about digital output. I used 2.4 MHZ ramp wave and 25MHZ clock both are 1.0Vpp.

 

(Figure 1  . labview)

(Figure 2. Visual analog)

I noticed that these data comes out when the set of number format is offset binary.

 

In matlab sample that I found in forum said separate odd and even column, multiple even column, and then add odd and multipled even column. But the result doesn't come out. Because the even column of data is all FF(hex).

 

The first question is how can I change the offset binary data to  two's complement data? Or do I just change the output mode of ad9613?

 

The second question is, how can I change this? Because when I get the data from labview, It's all decimal number.  And the difference of figure 1 and 2 , how can I change amplitude like visual analog?

 

The third question is, this is actually extension of second question, How can I change the digital data in labview to 12 bit data? I tried to change to binary, it was 16bit data.

 

Sorry about short English.

 

From, 

 

Taehyung 

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Re: ADV7623 scale text

March 19, 2018, 5:25 am
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Hi,

 Here we have verified in our side,but we could able to do TBOX scaling with increased font.

 Do you have one of our evaluation board?

 If so,Please verify in your side,before moving to some controller.

 

To change the font scale, is there only the register TBOX_H_SCALE and TBOX_V_SCALE to change?

Yes.

 

Thanks,

Poornima

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Re: LT8650S using dual channel different output cyrrent

March 19, 2018, 5:40 am
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Hello

Additional query for start-up dropout viltage.

Are there any problem on LT8650S model?

 

Please check the attached file. "LT8650S_startup_dropout_voltage.pdf"

I've confirm using LTspice below condition.

Vin=0 to10V sweep

Vout2=5V / 5A

 

When the OUT2 voltage become 5V, VIN1 is above 9V.

It seems very large, because VDS is below 500mV @5A and start-up dropout

voltage is below 1V @1A in the datasheet. (P5 Switch VDS, P8 Start-Up Dropout Performance)

 

Best Regards

T.Kamino

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Re: ADV7180: video quality difference between 8bit and 16bit

March 19, 2018, 5:43 am
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Hi,

 The 16-bit is same as the 8-bit except splitting the pixel up into luma and chrome channels with LLC = pixel rate,while 8-bit LLC = 2 x pixel rate.

 Please refer Page76 in ADV7180 datasheet.

 

Thanks,

Poornima

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Re: Hittite HMC-T2220 PLL loss of lock

March 19, 2018, 5:47 am
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I have contacted Camille there in China, he is an excellent resource for ADI. he can help you get an RMA for this box and get it to the repair facility. 

will you please send me a separate email so I can include Camille. 

 

jarrett.liner@analog.com  (USA)

Camille.Huin@analog.com  (China)

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Re: Using extension headers on ADALM-PLUTO

March 19, 2018, 5:48 am
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4. The Zynq extension header labels match zynq pin labels, so they are reconfigurable, they will be configured by the bootloader and bitstream and you would have to look at those to be sure what they do.  It's likely the MIO pins would be configured as Zynq built-in GPIO and map to linux GPIO /sys/class/gpio/gpiochip906 and gpio906,915,916,917,954,955,959.  For the three L*P and L*N pins you would have to look at the bitstream, they could be pretty much anything!

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Re: AD9689 Eval

March 19, 2018, 7:12 am
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Yes, there is a signal at J3. I probed it, and even increased the level a few dB. No matter what we try, we cannot get LED 5 or 6 to come on. We even tried higher frequencies, 2GHz for ADC and 500MHz for REF.

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Re: lwIP copy tx vs DMA

March 19, 2018, 7:18 am
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Yes, the implementation between the Ethernet driver and lwIP.  (nifce_driver.c) for the Blackfin.

  • RX, Ethernet driver buffers are copied.  For example, RX packet is received, then a lwip packet is allocated and copied. 
    • The function is:
      • process_rcvd_packets
        • allocate lwIP buffer, then copy the received packet from driver into lwip packet.
  • TX,
    • lwip pb_buffer is copied into an Ethernet TX buffer, this is done in low_level_ouput.

 

The goal is to remove the Blackfin CPU copying the packets from lwIP pubf to Ethernet TX buffer.  When streaming large packets, this does impact performance.

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Re: How to write my own low-level pin interrupt handler (BF70x, CCES 2.7.0)

March 19, 2018, 7:25 am
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How to capture Channel A and B of AD9208 simultaneously?

March 19, 2018, 7:29 am
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Hi all, 

I have connected the AD9208 with the FPGA board and is capturing channel A nicely. However I haven't managed to get channel B working (I have tried writing the register in ACE). Also I like to get both channels captured at the same time, is this possible in ACE or Matlab?

 

 

Regards,

Amin

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Cumulative Error calculation for a voltage reference - ADR435

February 12, 2014, 6:15 am
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Hi,

 

 

I am using ADR435 as a reference for a 18 Bit ADC(AD7631). The specification demands a detailed calculation of error introduced by the reference. I have done the error analysis in following way. Please confirm that the calculations are correct and acceptable.

 

Part No :ADR435

It is assumed that the initial accuracy is calibrated.

 

Temperature Variation : 3 ppm/DegC * 20 DegC = 60 ppm ( temperature variation is from 25 DegC to 45 DegC)

 

Line regulation : Consider +/-10% variation in input 15V, i.e 3V.

                  Vout = 20ppm/V * 3V = 60 ppm

 

Load Regulation : Rout = 15 ppm/mA = 75 mohm; Demanded current is 50uA. So, 75mohm * 50uA/5 = 0.75 ppm

 

Noise : 1/f noise ==> 8 uVp-p/6.6 = 1.21 uV rms /5V = 0.242 ppm

 

Temperature hysteresis : 20 ppm

 

Long term stability :  6 months ==> 6 * 30 *24 = 4320 hours ; 40 ppm * 4320 /1000 = 172.8 ppm

 

 

Total Variation in output after 6 months = 60 ppm + 60 ppm + 0.75 ppm + 0.242 ppm +  20 ppm + 172.8 ppm = 313.792 ppm

 

 

Clarification Needed:

1. While calculating "Long term stability" of this reference I have used the given specification linearly for every next 1000 hrs. But in some datasheets I have seen that the variation in Long term stability reduces in each cycle of 1000 hrs.

It is not provided in this datasheet. Could you please provide that information.

2. Please let me know if there is any wrong calculation.

3. Please provide me documents/application_notes related to voltage reference error calculations with respect to high precision ADC.

 

Thanks,

Jebas.

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Re: ADV7619 RXX_5V backfeed

March 19, 2018, 7:31 am
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Just to enhance what Poornima stated.  Each of those pins are ESD rated for 200V CDM which is good enough for assembly however the real world is much harsher so external ESB protection should be included such as diode bridges. Check our reference schematics to see how we did it.

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Re: ADV7619 RXX_5V backfeed

March 19, 2018, 7:26 am
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Hi,

  Yes,ESD protection and backdrive protection are important on each and every external signal line.

  Please refer HDMI port protection attachment.

 

Thanks,

Poornima

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Re: Update the AD9361 reference HDL design to use ILA?

March 19, 2018, 7:36 am
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Thank you Michael. Now I see where u-boot is located. However, when I run the build_boot_bin.sh script from Building the Zynq Linux kernel and devicetrees from source [Analog Devices Wiki], last step; I get the following error:

$ ./build_boot_bin.sh ./newboot/system_top.hdf ./newboot/u-boot-zed.elf
+ HDF_FILE=./newboot/system_top.hdf
+ UBOOT_FILE=./newboot/u-boot-zed.elf
+ BUILD_DIR=build_boot_bin
+ OUTPUT_DIR=output_boot_bin
+ echo ./newboot/system_top.hdf
+ grep -q .hdf
+ echo ./newboot/u-boot-zed.elf
+ grep -q -e .elf -e uboot
+ '[' '!' -f ./newboot/system_top.hdf ']'
+ '[' '!' -f ./newboot/u-boot-zed.elf ']'
+ command -v xsdk
+ command -v bootgen
+ rm -Rf build_boot_bin output_boot_bin
+ mkdir -p output_boot_bin
+ mkdir -p build_boot_bin
+ cp ./newboot/system_top.hdf build_boot_bin/
+ cp ./newboot/u-boot-zed.elf output_boot_bin/u-boot.elf
+ cp ./newboot/system_top.hdf output_boot_bin/
+ echo 'hsi open_hw_design ./newboot/system_top.hdf'
+ echo 'set cpu_name [lindex [hsi get_cells -filter {IP_TYPE==PROCESSOR}] 0]'
+ echo 'sdk setws ./build/sdk'
+ echo 'sdk createhw -name hw_0 -hwspec ./newboot/system_top.hdf'
+ echo 'sdk createapp -name fsbl -hwproject hw_0 -proc $cpu_name -os standalone -lang C -app {Zynq FSBL}'
+ echo 'configapp -app fsbl build-config release'
+ echo 'sdk projects -build -type all'
+ echo the_ROM_image:
+ echo '{'
+ echo '[bootloader] fsbl.elf'
+ echo system_top.bit
+ echo u-boot.elf
+ echo '}'
+ cd build_boot_bin
+ xsdk -batch -source create_fsbl_project.tcl
ERROR: [HDF 64-5] File not found - ./newboot/system_top.hdf
ERROR: [Hsi 55-1451] Error: running open_hw_design.
ERROR: [Common 17-39] 'hsi::open_hw_design' failed due to earlier errors.

 

    while executing
"hsi open_hw_design ./newboot/system_top.hdf"
    (file "create_fsbl_project.tcl" line 1)

 

Do I have to run this manually in SDK?

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Re: Update the AD9361 reference HDL design to use ILA?

March 19, 2018, 7:46 am
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Can you try to run the script with absolute paths?

 

$ ./build_boot_bin.sh /home/user/some/newboot/system_top.hdf /home/user/some/newboot/u-boot-zed.elf

 

-Michael

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Re: Power consumption of LTC2620 Vref

March 19, 2018, 7:47 am
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Hiroyuki.D   Yes, that is the way to calculate the current on the reference of the LTC2620.   If you are using 8 channels you it will be about 1.2mA 

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Re: can't find the Devicetree.dtb

March 20, 2018, 7:16 am
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Thanks for your patient and careful answer. I have the last problem it may be a silly one .It is which filesyetem I should choose when formatting the SD Card? FAT or FAT32?

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Re: adv7619 Brightness Settings

March 20, 2018, 7:17 am
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Hi,

 Have you configured the color controls registers according to reference script default settings?

 But still you facing the same,Please let us know.

 

Thanks,

Poornima

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Re: How to write my own low-level pin interrupt handler (BF70x, CCES 2.7.0)

March 20, 2018, 7:18 am
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I'm having some difficulty with the RTL interrupt support.

 

I am following the example in RTL-Level Interrupt Support for SHARC and Blackfin Processors. My code fragment looks like this:

adi_result = adi_int_InstallHandler (INTR_PINT2_BLOCK, NULL, /*callback param*/NULL, /*enable*/false);
printf ("adi_int_InstallHandler returned %ld\n", adi_result);

 

/* Call the RTL-level dispatcher register function to install the custom handler
** to replace the SSL-level dispatched handler.
*/

adi_result = adi_rtl_register_dispatched_handler (INTR_PINT2_BLOCK, MyISR, (adi_dispatched_callback_t) NULL);
printf ("adi_rtl_register_dispatched_handler returned %ld\n", adi_result);

 

/* Enable INTR_PINT2_BLOCK */
adi_result = adi_int_EnableInt (INTR_PINT2_BLOCK, true);
printf ("adi_int_EnableInt returned %ld\n", adi_result);

 

/* PINT2 can sense activity on Port C and Port A (maps into A and B in Assignment).*/
/* See PINT register definitions in adi_gpio_data_bf70x.c */
/* Map top half of Port A (optos) onto PINT2 byte 1 - B1MAP */
/* Map bottom half of Port C (SW 1-1) onto PINT2 byte 0 B0MAP thereby only requiring 16-bit access */
*pREG_PINT2_ASSIGN = 0x00000100u; // Opto 2 and 1 (pA11, 10) in B1MAP[11..10], SW1-0 PC_07 in B0MAP[7]
*pREG_PINT2_EDGE_SET = 0x00000c80u; // All edge sensitive
// *pREG_PINT2_MSK_SET = 0x00000c80u; // enable all three interrupts
*pREG_PINT2_MSK_SET = 0x00000080u; // enable pin interrupt for switch 0 (PC_07) only for test

I want to register the interrupt for Pin Interrupt block 2 (PINT2) but adi_rtl_register_dispatched_handler() returns -1.

I assume that it's because INTR_PINT2_BLOCK (== 22 decimal) is not a valid value for the parameter 'iid'.

 

The help says:

  adi_int_InstallHandler

  • iid - Interrupt ID. For system interrupts this is the system interrupt ID (also referred to as peripheral interrupt ID in the Hardware Reference manuals). This is a unique number to identify a particular interrupt. Refer to the Hardware Reference manual for your processor to find the number for a specific interrupt

According the the hardware reference manual for BF706, the interrupt number for PINT2_BLOCK is 22 (table 8-2, p226). It is accepted as a valid 'iid' by both adi_int_InstallHandler() and adi_int_EnableInt() but not by  adi_rtl_register_dispatched_handler().

Why not? Or... what is the correct interrupt ID for PINT2?

 

Many thanks.

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Re: ZC702 +FMCOMMS3 with Petalinux-2016.2

March 20, 2018, 7:19 am
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Hello Michael,

 

 

We are transmitting from one ad9361  and receiving from another. So, we

1) Removed Y101 crystal from one ad9361 (acting as receiver)

2) Tapped the  CLK_OUT pin of other ad9361  (acting as transmitter) and giving it to the REF_CLK (J105)port of the receiving ad9361.

 

We made these changes in the NO_OS 

1) xo_disable_use_ext_refclk_enable  This parameter is set as 1 in the receiving side(no crystal)

2)clk_output_mode_select This paramter is set as 1 in the transmitting side (with crystal)

 

With the above changes, we are able to receive and decode properly. 

 

When the Linux is running on the Zynq board, 

1)adi,xo-disable-use-ext-refclk-enable; This parameter is set as 1 in the dts file of  receiver(no crystal)

2)adi,clk-output-mode-select=<0x1>; This line is added In the dts file of the transmitter(ad9361 with crystal)

 

Do we need to make any other changes in the dts files to make it work?

 

Also, we are planning to use 10MHZ external clock for both of the ad9361 s through Ettus Octaclock-g. Do we need to make any additional changes before starting with this?

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